ENTROPY_SRC Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 111.148us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 13.000s 129.679us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 35.254us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 637.714us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 830.838us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 254.041us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 35.254us 20 20 100.00
entropy_src_csr_aliasing 8.000s 830.838us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 111.148us 50 50 100.00
entropy_src_rng 4.583m 10.052ms 300 300 100.00
entropy_src_fw_ov 2.367m 5.061ms 292 300 97.33
V2 firmware_mode entropy_src_fw_ov 2.367m 5.061ms 292 300 97.33
V2 rng_mode entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.950m 10.046ms 390 400 97.50
V2 health_checks entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2 conditioning entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2 interrupts entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2 alerts entropy_src_rng 4.583m 10.052ms 300 300 100.00
entropy_src_functional_alerts 13.000s 100.534us 50 50 100.00
V2 stress_all entropy_src_stress_all 13.000s 985.076us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 26.000s 407.862us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 62.461us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 53.278us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 144.234us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 144.234us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 13.000s 129.679us 5 5 100.00
entropy_src_csr_rw 4.000s 35.254us 20 20 100.00
entropy_src_csr_aliasing 8.000s 830.838us 5 5 100.00
entropy_src_same_csr_outstanding 13.000s 41.569us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 13.000s 129.679us 5 5 100.00
entropy_src_csr_rw 4.000s 35.254us 20 20 100.00
entropy_src_csr_aliasing 8.000s 830.838us 5 5 100.00
entropy_src_same_csr_outstanding 13.000s 41.569us 20 20 100.00
V2 TOTAL 2235 2290 97.60
V2S tl_intg_err entropy_src_sec_cm 6.000s 68.334us 5 5 100.00
entropy_src_tl_intg_err 7.000s 169.708us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.583m 10.052ms 300 300 100.00
entropy_src_cfg_regwen 10.000s 62.807us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.583m 10.052ms 300 300 100.00
entropy_src_fw_ov 2.367m 5.061ms 292 300 97.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 68.334us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 68.334us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.583m 10.052ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 68.334us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 68.334us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.917m 10.012ms 963 1000 96.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 100.534us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 169.708us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.583m 10.024ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 967.368us 43 50 86.00
TOTAL 2508 2570 97.59

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.42 98.17 95.37 98.33 95.84 88.05 96.88 90.46 57.95

Failure Buckets

Past Results