ENTROPY_SRC Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 64.528us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 7.000s 24.386us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 12.000s 22.184us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 360.679us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 10.000s 457.942us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 62.772us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 12.000s 22.184us 20 20 100.00
entropy_src_csr_aliasing 10.000s 457.942us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 64.528us 50 50 100.00
entropy_src_rng 5.100m 10.068ms 299 300 99.67
entropy_src_fw_ov 2.533m 5.028ms 296 300 98.67
V2 firmware_mode entropy_src_fw_ov 2.533m 5.028ms 296 300 98.67
V2 rng_mode entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.167m 10.080ms 388 400 97.00
V2 health_checks entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2 conditioning entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2 interrupts entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2 alerts entropy_src_rng 5.100m 10.068ms 299 300 99.67
entropy_src_functional_alerts 5.000s 68.162us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 406.928us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 1.446ms 50 50 100.00
V2 intr_test entropy_src_intr_test 12.000s 36.722us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 60.038us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 246.661us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 246.661us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 7.000s 24.386us 5 5 100.00
entropy_src_csr_rw 12.000s 22.184us 20 20 100.00
entropy_src_csr_aliasing 10.000s 457.942us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 470.193us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 7.000s 24.386us 5 5 100.00
entropy_src_csr_rw 12.000s 22.184us 20 20 100.00
entropy_src_csr_aliasing 10.000s 457.942us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 470.193us 20 20 100.00
V2 TOTAL 2245 2290 98.03
V2S tl_intg_err entropy_src_sec_cm 5.000s 389.711us 5 5 100.00
entropy_src_tl_intg_err 9.000s 67.580us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.100m 10.068ms 299 300 99.67
entropy_src_cfg_regwen 4.000s 20.968us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.100m 10.068ms 299 300 99.67
entropy_src_fw_ov 2.533m 5.028ms 296 300 98.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
entropy_src_sec_cm 5.000s 389.711us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
entropy_src_sec_cm 5.000s 389.711us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.100m 10.068ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
entropy_src_sec_cm 5.000s 389.711us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
entropy_src_sec_cm 5.000s 389.711us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.650m 10.022ms 972 1000 97.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 68.162us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 9.000s 67.580us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.767m 10.056ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 20.000s 851.027us 44 50 88.00
TOTAL 2518 2570 97.98

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.52 98.17 95.37 98.33 95.84 88.00 96.88 90.46 58.38

Failure Buckets

Past Results