ENTROPY_SRC Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 9.000s 22.300us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 7.000s 36.235us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 12.000s 46.688us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 12.000s 322.857us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 218.676us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 13.000s 20.510us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 12.000s 46.688us 20 20 100.00
entropy_src_csr_aliasing 8.000s 218.676us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 9.000s 22.300us 50 50 100.00
entropy_src_rng 4.717m 10.058ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.032ms 294 300 98.00
V2 firmware_mode entropy_src_fw_ov 2.450m 5.032ms 294 300 98.00
V2 rng_mode entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.017m 10.063ms 391 400 97.75
V2 health_checks entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2 conditioning entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2 interrupts entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2 alerts entropy_src_rng 4.717m 10.058ms 300 300 100.00
entropy_src_functional_alerts 9.000s 560.421us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.000s 401.235us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 27.000s 1.350ms 50 50 100.00
V2 intr_test entropy_src_intr_test 16.000s 23.920us 50 50 100.00
V2 alert_test entropy_src_alert_test 7.000s 45.411us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 10.000s 436.613us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 10.000s 436.613us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 7.000s 36.235us 5 5 100.00
entropy_src_csr_rw 12.000s 46.688us 20 20 100.00
entropy_src_csr_aliasing 8.000s 218.676us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 85.423us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 7.000s 36.235us 5 5 100.00
entropy_src_csr_rw 12.000s 46.688us 20 20 100.00
entropy_src_csr_aliasing 8.000s 218.676us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 85.423us 20 20 100.00
V2 TOTAL 2238 2290 97.73
V2S tl_intg_err entropy_src_sec_cm 6.000s 155.710us 5 5 100.00
entropy_src_tl_intg_err 12.000s 174.945us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.717m 10.058ms 300 300 100.00
entropy_src_cfg_regwen 8.000s 66.295us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.717m 10.058ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.032ms 294 300 98.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
entropy_src_sec_cm 6.000s 155.710us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
entropy_src_sec_cm 6.000s 155.710us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.717m 10.058ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
entropy_src_sec_cm 6.000s 155.710us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
entropy_src_sec_cm 6.000s 155.710us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.217m 10.013ms 963 1000 96.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 560.421us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 12.000s 174.945us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.633m 10.029ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 23.000s 1.936ms 41 50 82.00
TOTAL 2508 2570 97.59

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.81 98.21 95.47 98.36 95.84 88.07 96.88 90.46 59.46

Failure Buckets

Past Results