ENTROPY_SRC Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 29.975us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 101.213us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 59.101us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 3.179ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 683.867us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 35.154us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 59.101us 20 20 100.00
entropy_src_csr_aliasing 7.000s 683.867us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 29.975us 50 50 100.00
entropy_src_rng 5.050m 10.059ms 298 300 99.33
entropy_src_fw_ov 2.417m 5.025ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.417m 5.025ms 289 300 96.33
V2 rng_mode entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 9.550m 10.050ms 388 400 97.00
V2 health_checks entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2 conditioning entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2 interrupts entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2 alerts entropy_src_rng 5.050m 10.059ms 298 300 99.33
entropy_src_functional_alerts 5.000s 56.578us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 2.502ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 356.929us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 62.550us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 36.117us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 127.132us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 127.132us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 101.213us 5 5 100.00
entropy_src_csr_rw 3.000s 59.101us 20 20 100.00
entropy_src_csr_aliasing 7.000s 683.867us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 89.000us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 101.213us 5 5 100.00
entropy_src_csr_rw 3.000s 59.101us 20 20 100.00
entropy_src_csr_aliasing 7.000s 683.867us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 89.000us 20 20 100.00
V2 TOTAL 2228 2290 97.29
V2S tl_intg_err entropy_src_sec_cm 4.000s 92.019us 5 5 100.00
entropy_src_tl_intg_err 7.000s 213.614us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.050m 10.059ms 298 300 99.33
entropy_src_cfg_regwen 4.000s 63.299us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.050m 10.059ms 298 300 99.33
entropy_src_fw_ov 2.417m 5.025ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
entropy_src_sec_cm 4.000s 92.019us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
entropy_src_sec_cm 4.000s 92.019us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.050m 10.059ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
entropy_src_sec_cm 4.000s 92.019us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
entropy_src_sec_cm 4.000s 92.019us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.383m 10.013ms 963 1000 96.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 56.578us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 213.614us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.817m 10.091ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 19.000s 516.817us 43 50 86.00
TOTAL 2501 2570 97.32

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.64 98.21 95.47 98.36 95.84 88.10 96.88 90.46 58.73

Failure Buckets

Past Results