ENTROPY_SRC Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 39.781us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 156.809us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 76.003us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 4.541ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 220.181us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 57.759us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 76.003us 20 20 100.00
entropy_src_csr_aliasing 8.000s 220.181us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 39.781us 50 50 100.00
entropy_src_rng 4.667m 10.055ms 298 300 99.33
entropy_src_fw_ov 2.500m 5.083ms 291 300 97.00
V2 firmware_mode entropy_src_fw_ov 2.500m 5.083ms 291 300 97.00
V2 rng_mode entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.817m 10.044ms 389 400 97.25
V2 health_checks entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2 conditioning entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2 interrupts entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2 alerts entropy_src_rng 4.667m 10.055ms 298 300 99.33
entropy_src_functional_alerts 5.000s 58.364us 50 50 100.00
V2 stress_all entropy_src_stress_all 13.000s 519.450us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 1.317ms 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 22.807us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 19.718us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 122.398us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 122.398us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 156.809us 5 5 100.00
entropy_src_csr_rw 3.000s 76.003us 20 20 100.00
entropy_src_csr_aliasing 8.000s 220.181us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 103.046us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 156.809us 5 5 100.00
entropy_src_csr_rw 3.000s 76.003us 20 20 100.00
entropy_src_csr_aliasing 8.000s 220.181us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 103.046us 20 20 100.00
V2 TOTAL 2231 2290 97.42
V2S tl_intg_err entropy_src_sec_cm 4.000s 145.220us 5 5 100.00
entropy_src_tl_intg_err 6.000s 124.360us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.667m 10.055ms 298 300 99.33
entropy_src_cfg_regwen 8.000s 47.981us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.667m 10.055ms 298 300 99.33
entropy_src_fw_ov 2.500m 5.083ms 291 300 97.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
entropy_src_sec_cm 4.000s 145.220us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
entropy_src_sec_cm 4.000s 145.220us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.667m 10.055ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
entropy_src_sec_cm 4.000s 145.220us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
entropy_src_sec_cm 4.000s 145.220us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.333m 10.012ms 963 1000 96.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 58.364us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 124.360us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.750m 10.028ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 37.000s 516.960us 44 50 88.00
TOTAL 2505 2570 97.47

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.55 98.21 95.47 98.36 95.84 88.32 96.88 90.46 58.24

Failure Buckets

Past Results