ENTROPY_SRC Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 14.000s 58.211us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 166.191us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 92.221us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 538.091us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 134.926us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 33.607us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 92.221us 20 20 100.00
entropy_src_csr_aliasing 8.000s 134.926us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 14.000s 58.211us 50 50 100.00
entropy_src_rng 4.550m 10.054ms 300 300 100.00
entropy_src_fw_ov 2.317m 5.024ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.317m 5.024ms 289 300 96.33
V2 rng_mode entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.817m 10.080ms 389 400 97.25
V2 health_checks entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2 conditioning entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2 interrupts entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2 alerts entropy_src_rng 4.550m 10.054ms 300 300 100.00
entropy_src_functional_alerts 15.000s 66.067us 50 50 100.00
V2 stress_all entropy_src_stress_all 15.000s 123.504us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 343.303us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 67.911us 50 50 100.00
V2 alert_test entropy_src_alert_test 13.000s 44.906us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 2.682ms 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 2.682ms 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 166.191us 5 5 100.00
entropy_src_csr_rw 4.000s 92.221us 20 20 100.00
entropy_src_csr_aliasing 8.000s 134.926us 5 5 100.00
entropy_src_same_csr_outstanding 10.000s 167.784us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 166.191us 5 5 100.00
entropy_src_csr_rw 4.000s 92.221us 20 20 100.00
entropy_src_csr_aliasing 8.000s 134.926us 5 5 100.00
entropy_src_same_csr_outstanding 10.000s 167.784us 20 20 100.00
V2 TOTAL 2229 2290 97.34
V2S tl_intg_err entropy_src_sec_cm 4.000s 92.733us 5 5 100.00
entropy_src_tl_intg_err 7.000s 199.740us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.550m 10.054ms 300 300 100.00
entropy_src_cfg_regwen 9.000s 18.701us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.550m 10.054ms 300 300 100.00
entropy_src_fw_ov 2.317m 5.024ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 92.733us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 92.733us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.550m 10.054ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 92.733us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 92.733us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.583m 10.013ms 961 1000 96.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 15.000s 66.067us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 199.740us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.367m 10.046ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 4.826ms 46 50 92.00
TOTAL 2505 2570 97.47

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.73 98.23 95.53 98.38 95.88 88.12 97.92 90.46 58.99

Failure Buckets

Past Results