ENTROPY_SRC Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 33.775us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 61.495us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 31.033us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 817.791us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 466.101us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 41.397us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 31.033us 20 20 100.00
entropy_src_csr_aliasing 7.000s 466.101us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 33.775us 50 50 100.00
entropy_src_rng 4.533m 10.082ms 300 300 100.00
entropy_src_fw_ov 2.283m 5.044ms 283 300 94.33
V2 firmware_mode entropy_src_fw_ov 2.283m 5.044ms 283 300 94.33
V2 rng_mode entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.783m 10.023ms 385 400 96.25
V2 health_checks entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2 conditioning entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2 interrupts entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2 alerts entropy_src_rng 4.533m 10.082ms 300 300 100.00
entropy_src_functional_alerts 14.000s 63.683us 50 50 100.00
V2 stress_all entropy_src_stress_all 19.000s 2.994ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 27.000s 3.977ms 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 16.279us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 122.403us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 1.908ms 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 1.908ms 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 61.495us 5 5 100.00
entropy_src_csr_rw 8.000s 31.033us 20 20 100.00
entropy_src_csr_aliasing 7.000s 466.101us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 271.687us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 61.495us 5 5 100.00
entropy_src_csr_rw 8.000s 31.033us 20 20 100.00
entropy_src_csr_aliasing 7.000s 466.101us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 271.687us 20 20 100.00
V2 TOTAL 2230 2290 97.38
V2S tl_intg_err entropy_src_sec_cm 8.000s 305.511us 5 5 100.00
entropy_src_tl_intg_err 6.000s 806.598us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.533m 10.082ms 300 300 100.00
entropy_src_cfg_regwen 12.000s 33.986us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.533m 10.082ms 300 300 100.00
entropy_src_fw_ov 2.283m 5.044ms 283 300 94.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
entropy_src_sec_cm 8.000s 305.511us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
entropy_src_sec_cm 8.000s 305.511us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.533m 10.082ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
entropy_src_sec_cm 8.000s 305.511us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
entropy_src_sec_cm 8.000s 305.511us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.083m 10.013ms 972 1000 97.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 63.683us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 806.598us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.450m 10.087ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 1.019ms 43 50 86.00
TOTAL 2503 2570 97.39

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.28 98.17 95.37 98.33 95.84 88.07 96.88 90.46 57.38

Failure Buckets

Past Results