ENTROPY_SRC Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 33.165us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 83.711us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 31.219us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 3.474ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 10.000s 1.067ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 55.342us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 31.219us 20 20 100.00
entropy_src_csr_aliasing 10.000s 1.067ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 33.165us 50 50 100.00
entropy_src_rng 5.733m 10.078ms 300 300 100.00
entropy_src_fw_ov 2.733m 5.070ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.733m 5.070ms 289 300 96.33
V2 rng_mode entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.417m 10.027ms 398 400 99.50
V2 health_checks entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2 conditioning entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2 interrupts entropy_src_rng 5.733m 10.078ms 300 300 100.00
entropy_src_intr 25.000s 4.373ms 50 50 100.00
V2 alerts entropy_src_rng 5.733m 10.078ms 300 300 100.00
entropy_src_functional_alerts 9.000s 61.106us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.000s 1.837ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 717.904us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 45.098us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 35.796us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 527.265us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 527.265us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 83.711us 5 5 100.00
entropy_src_csr_rw 4.000s 31.219us 20 20 100.00
entropy_src_csr_aliasing 10.000s 1.067ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 1.437ms 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 83.711us 5 5 100.00
entropy_src_csr_rw 4.000s 31.219us 20 20 100.00
entropy_src_csr_aliasing 10.000s 1.067ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 1.437ms 20 20 100.00
V2 TOTAL 2292 2340 97.95
V2S tl_intg_err entropy_src_sec_cm 3.000s 111.259us 5 5 100.00
entropy_src_tl_intg_err 7.000s 177.899us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.733m 10.078ms 300 300 100.00
entropy_src_cfg_regwen 4.000s 16.674us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 5.733m 10.078ms 300 300 100.00
entropy_src_fw_ov 2.733m 5.070ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
entropy_src_sec_cm 3.000s 111.259us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
entropy_src_sec_cm 3.000s 111.259us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.733m 10.078ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
entropy_src_sec_cm 3.000s 111.259us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
entropy_src_sec_cm 3.000s 111.259us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.333m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 61.106us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 177.899us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.133m 10.017ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2522 2570 98.13

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.14 98.19 95.43 98.36 95.79 96.71 96.88 90.48 95.70

Failure Buckets

Past Results