ENTROPY_SRC Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 19.000s 61.381us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 46.608us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 62.992us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 1.589ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 1.786ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 36.418us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 62.992us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.786ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 19.000s 61.381us 50 50 100.00
entropy_src_rng 5.483m 10.029ms 299 300 99.67
entropy_src_fw_ov 2.933m 5.061ms 291 300 97.00
V2 firmware_mode entropy_src_fw_ov 2.933m 5.061ms 291 300 97.00
V2 rng_mode entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.600m 10.097ms 398 400 99.50
V2 health_checks entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2 conditioning entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2 interrupts entropy_src_rng 5.483m 10.029ms 299 300 99.67
entropy_src_intr 31.000s 1.014ms 50 50 100.00
V2 alerts entropy_src_rng 5.483m 10.029ms 299 300 99.67
entropy_src_functional_alerts 19.000s 108.398us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 488.065us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 32.000s 5.522ms 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 20.802us 50 50 100.00
V2 alert_test entropy_src_alert_test 13.000s 32.509us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 290.355us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 290.355us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 46.608us 5 5 100.00
entropy_src_csr_rw 4.000s 62.992us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.786ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 98.756us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 46.608us 5 5 100.00
entropy_src_csr_rw 4.000s 62.992us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.786ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 98.756us 20 20 100.00
V2 TOTAL 2295 2340 98.08
V2S tl_intg_err entropy_src_sec_cm 13.000s 149.503us 5 5 100.00
entropy_src_tl_intg_err 7.000s 208.860us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.483m 10.029ms 299 300 99.67
entropy_src_cfg_regwen 9.000s 17.674us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.483m 10.029ms 299 300 99.67
entropy_src_fw_ov 2.933m 5.061ms 291 300 97.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
entropy_src_sec_cm 13.000s 149.503us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
entropy_src_sec_cm 13.000s 149.503us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.483m 10.029ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
entropy_src_sec_cm 13.000s 149.503us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
entropy_src_sec_cm 13.000s 149.503us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.433m 10.013ms 967 1000 96.70
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 19.000s 108.398us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 208.860us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.083m 10.103ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2525 2570 98.25

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.13 98.15 95.32 98.33 95.79 96.59 96.88 90.48 95.93

Failure Buckets

Past Results