ENTROPY_SRC Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 22.202us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 67.434us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 31.005us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 514.395us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 237.613us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 135.104us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 31.005us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.613us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 22.202us 50 50 100.00
entropy_src_rng 5.583m 10.019ms 298 300 99.33
entropy_src_fw_ov 3.100m 5.054ms 287 300 95.67
V2 firmware_mode entropy_src_fw_ov 3.100m 5.054ms 287 300 95.67
V2 rng_mode entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 9.783m 10.017ms 394 400 98.50
V2 health_checks entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2 conditioning entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2 interrupts entropy_src_rng 5.583m 10.019ms 298 300 99.33
entropy_src_intr 33.000s 2.042ms 50 50 100.00
V2 alerts entropy_src_rng 5.583m 10.019ms 298 300 99.33
entropy_src_functional_alerts 5.000s 91.309us 50 50 100.00
V2 stress_all entropy_src_stress_all 14.000s 745.994us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 1.191ms 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 32.093us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 35.182us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 168.107us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 168.107us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 67.434us 5 5 100.00
entropy_src_csr_rw 4.000s 31.005us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.613us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 174.661us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 67.434us 5 5 100.00
entropy_src_csr_rw 4.000s 31.005us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.613us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 174.661us 20 20 100.00
V2 TOTAL 2278 2340 97.35
V2S tl_intg_err entropy_src_sec_cm 3.000s 55.906us 5 5 100.00
entropy_src_tl_intg_err 7.000s 177.188us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.583m 10.019ms 298 300 99.33
entropy_src_cfg_regwen 12.000s 86.298us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.583m 10.019ms 298 300 99.33
entropy_src_fw_ov 3.100m 5.054ms 287 300 95.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
entropy_src_sec_cm 3.000s 55.906us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
entropy_src_sec_cm 3.000s 55.906us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.583m 10.019ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
entropy_src_sec_cm 3.000s 55.906us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
entropy_src_sec_cm 3.000s 55.906us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.750m 10.012ms 959 1000 95.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 91.309us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 177.188us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.267m 10.020ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2508 2570 97.59

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.08 98.15 95.32 98.33 95.79 96.59 96.88 90.48 95.47

Failure Buckets

Past Results