FLASH_CTRL Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.667m	51.221us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.790s	51.860us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.360s	40.890us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.242m	2.383ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.036m	1.576ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.250s	39.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
		flash_ctrl_csr_aliasing	1.036m	1.576ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.460s	47.250us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.420s	62.101us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.690s	222.041us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.665m	58.471us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	28.761m	83.720ms	3	3	100.00
		flash_ctrl_hw_rma_reset	13.780m	190.196ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.720s	24.704us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	38.661m	241.218ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.399m	3.420ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	22.990s	170.023us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	44.127m	216.521ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.490m	1.409ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.320s	108.947us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.890s	159.610us	39	40	97.50
		flash_ctrl_re_evict	40.590s	401.578us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.120m	1.451ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.120m	1.451ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.443m	12.524ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.070s	1.165ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	26.628m	4.415ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.383m	11.649ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.416m	1.823ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.697m	3.692ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.790s	26.846us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.083m	2.489ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.280s	24.659us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.190s	29.916us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.618m	335.729us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.162m	12.786ms	50	50	100.00
		flash_ctrl_otp_reset	2.288m	45.133us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	28.761m	83.720ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	6.875m	11.212ms	40	40	100.00
		flash_ctrl_intr_wr	2.124m	74.342ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	12.005m	211.525ms	39	40	97.50
		flash_ctrl_intr_wr_slow_flash	10.948m	222.389ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.653m	33.825ms	18	20	90.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	51.850s	2.977ms	3	5	60.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.770s	22.589us	5	5	100.00
		flash_ctrl_ro_derr	6.580m	1.752ms	10	10	100.00
		flash_ctrl_rw_derr	29.278m	6.390ms	10	10	100.00
		flash_ctrl_derr_detect	1.906m	410.695us	5	5	100.00
		flash_ctrl_integrity	30.598m	91.323ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.890s	35.197us	5	5	100.00
		flash_ctrl_ro_serr	6.331m	3.682ms	10	10	100.00
		flash_ctrl_rw_serr	27.799m	56.363ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.360m	768.309us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.373m	1.685ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.446m	9.806ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.230s	238.464us	1	1	100.00
		flash_ctrl_read_word_sweep	13.250s	14.245us	1	1	100.00
		flash_ctrl_ro	5.017m	1.940ms	20	20	100.00
		flash_ctrl_rw	26.596m	10.498ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.920s	292.676us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.247m	71.745ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.503m	10.005ms	19	20	95.00
V2	alert_test	flash_ctrl_alert_test	14.660s	477.686us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.770s	32.492us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.800s	202.967us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.800s	202.967us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.360s	40.890us	5	5	100.00
		flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
		flash_ctrl_csr_aliasing	1.036m	1.576ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.640s	192.142us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.360s	40.890us	5	5	100.00
		flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
		flash_ctrl_csr_aliasing	1.036m	1.576ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.640s	192.142us	20	20	100.00
V2		TOTAL			1003	1013	99.01
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.977m	267.738us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.017m	1.026ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.017m	1.026ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.017m	1.026ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.630s	503.730us	3	3	100.00
		flash_ctrl_wr_intg	14.960s	234.902us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.667m	51.221us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.288m	45.133us	79	80	98.75
		flash_ctrl_disable	23.280s	24.659us	50	50	100.00
		flash_ctrl_sec_info_access	1.472m	4.400ms	50	50	100.00
		flash_ctrl_connect	16.190s	29.916us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.230s	324.079us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.920s	415.058us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.722m	143.504us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.280s	24.659us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.630s	503.730us	3	3	100.00
		flash_ctrl_access_after_disable	13.920s	39.830us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.280s	24.659us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.070s	1.165ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	26.596m	10.498ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	27.799m	56.363ms	10	10	100.00
		flash_ctrl_rw_derr	29.278m	6.390ms	10	10	100.00
		flash_ctrl_integrity	30.598m	91.323ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	28.761m	83.720ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.550s	25.167us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.590s	42.446us	1	5	20.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.140s	25.242us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	4.010ms	5	5	100.00
V2S		TOTAL			138	144	95.83
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.530s	82.177us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1262	1278	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	9	75.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.51	95.48	94.31	98.95	92.52	97.30	98.41	98.62

Failure Buckets

Offending '(!$isunknown(mem_tl_o.d_valid))' has 3 failures:

Test flash_ctrl_phy_host_grant_err has 3 failures.

0.flash_ctrl_phy_host_grant_err.3104220715
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 6023.2 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 6023.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_phy_host_grant_err.1097448584
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 4700.9 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 4700.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:620) [csr_utils::mem_rd] Timeout waiting to mem_rd flash_ctrl_core_reg_block.rd_fifo (addr=*) has 2 failures:

Test flash_ctrl_mid_op_rst has 2 failures.

0.flash_ctrl_mid_op_rst.2352787419
Line 724, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest/run.log

  UVM_FATAL @ 2977372.9 ns: (csr_utils_pkg.sv:620) [csr_utils::mem_rd] Timeout waiting to mem_rd flash_ctrl_core_reg_block.rd_fifo (addr=0x0)
  UVM_INFO @ 2977372.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_mid_op_rst.2260455420
Line 693, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest/run.log

  UVM_FATAL @ 3691821.7 ns: (csr_utils_pkg.sv:620) [csr_utils::mem_rd] Timeout waiting to mem_rd flash_ctrl_core_reg_block.rd_fifo (addr=0x0)
  UVM_INFO @ 3691821.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 2 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 6.flash_ctrl_intr_wr_slow_flash.1266573030
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_intr_rd_slow_flash has 1 failures.
  - 9.flash_ctrl_intr_rd_slow_flash.652102564
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_std_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 0.flash_ctrl_wr_intg.304680463
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 25545.1 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_std_err did not trigger max_delay:2000
  UVM_INFO @ 25545.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 1.flash_ctrl_phy_host_grant_err.2560422532
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 95151.6 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 95151.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:232) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.731978232
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 12538.9 ns: (flash_otf_item.sv:232) [rd_scr] ecc error is detected
  UVM_INFO @ 12538.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 4.flash_ctrl_full_mem_access.1479714356
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:b8c8737b-d3e6-4f6e-a90e-98225a906a8a
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 4.flash_ctrl_rw_evict_all_en.577683653
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 8699.2 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8699.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 1 failures.
  - 12.flash_ctrl_hw_prog_rma_wipe_err.1114192606
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10005241.5 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28856 [0x70b8])
  UVM_INFO @ 10005241.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_invalid_op has 1 failures.
  - 15.flash_ctrl_invalid_op.2859768504
    Line 1402, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest/run.log
```
  UVM_ERROR @ 691622.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 691622.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_invalid_op has 1 failures.
  - 17.flash_ctrl_invalid_op.1606452238
    Line 5153, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest/run.log
```
  UVM_ERROR @ 7343032.0 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 7343032.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'dst_req_o' has 1 failures:

Test flash_ctrl_otp_reset has 1 failures.

52.flash_ctrl_otp_reset.584358130
Line 343, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest/run.log

      Offending 'dst_req_o'
  UVM_ERROR @ 15074.1 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 15074.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---