FLASH_CTRL Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 3.607m 37.124us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.090s 14.599us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 38.820s 153.807us 4 5 80.00
V1 csr_rw flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.214m 2.468ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.047m 1.236ms 4 5 80.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.220s 49.288us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
flash_ctrl_csr_aliasing 1.047m 1.236ms 4 5 80.00
V1 mem_walk flash_ctrl_mem_walk 13.310s 27.700us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.670s 15.974us 5 5 100.00
V1 TOTAL 117 120 97.50
V2 sw_op flash_ctrl_sw_op 26.400s 205.947us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 1.533m 216.289us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 32.471m 552.004ms 3 3 100.00
flash_ctrl_hw_rma_reset 14.407m 160.187ms 20 20 100.00
flash_ctrl_lcmgr_intg 14.300s 16.095us 19 20 95.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 47.801m 290.731ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 7.980m 4.429ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 1.157m 748.407us 30 30 100.00
V2 full_memory_access flash_ctrl_full_mem_access 42.808m 325.454ms 2 5 40.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 2.225m 5.726ms 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 39.630s 2.258ms 39 40 97.50
flash_ctrl_rw_evict_all_en 37.860s 483.406us 39 40 97.50
flash_ctrl_re_evict 41.270s 153.735us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.314m 1.424ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.314m 1.424ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 21.045m 220.153ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 29.790s 1.702ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 20.564m 5.863ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 39.926m 8.822ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 15.817m 3.645ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 50.770m 2.087ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.610s 46.127us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 3.372m 3.040ms 5 5 100.00
V2 flash_ctrl_disable flash_ctrl_disable 54.488m 120.022ms 45 50 90.00
V2 flash_ctrl_connect flash_ctrl_connect 16.330s 20.941us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 27.299m 509.344us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 3.671m 11.567ms 50 50 100.00
flash_ctrl_otp_reset 2.248m 39.394us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 32.471m 552.004ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 2.944m 19.899ms 40 40 100.00
flash_ctrl_intr_wr 2.054m 28.547ms 10 10 100.00
flash_ctrl_intr_rd_slow_flash 4.749m 36.953ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 10.094m 72.768ms 10 10 100.00
V2 invalid_op flash_ctrl_invalid_op 1.492m 6.446ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.200m 3.277ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.730s 133.201us 5 5 100.00
flash_ctrl_ro_derr 2.209m 2.768ms 10 10 100.00
flash_ctrl_rw_derr 10.203m 15.941ms 10 10 100.00
flash_ctrl_derr_detect 1.749m 113.670us 5 5 100.00
flash_ctrl_integrity 10.342m 16.440ms 5 5 100.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 23.030s 176.604us 5 5 100.00
flash_ctrl_ro_serr 2.220m 646.360us 10 10 100.00
flash_ctrl_rw_serr 8.977m 16.188ms 10 10 100.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.358m 1.547ms 5 5 100.00
V2 singlebit_err_address flash_ctrl_serr_address 1.605m 3.753ms 5 5 100.00
V2 scramble flash_ctrl_wo 3.341m 2.453ms 20 20 100.00
flash_ctrl_write_word_sweep 17.070s 238.278us 1 1 100.00
flash_ctrl_read_word_sweep 13.940s 41.688us 1 1 100.00
flash_ctrl_ro 2.008m 903.780us 20 20 100.00
flash_ctrl_rw 9.058m 6.362ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 36.200s 1.136ms 5 5 100.00
V2 rma_write_process_error flash_ctrl_rma_err 16.136m 160.733ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 4.553m 10.012ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.430s 166.110us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.280s 31.682us 49 50 98.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.210s 54.079us 19 20 95.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.210s 54.079us 19 20 95.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 38.820s 153.807us 4 5 80.00
flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
flash_ctrl_csr_aliasing 1.047m 1.236ms 4 5 80.00
flash_ctrl_same_csr_outstanding 35.470s 199.263us 19 20 95.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 38.820s 153.807us 4 5 80.00
flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
flash_ctrl_csr_aliasing 1.047m 1.236ms 4 5 80.00
flash_ctrl_same_csr_outstanding 35.470s 199.263us 19 20 95.00
V2 TOTAL 999 1013 98.62
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 15.730s 50.199us 19 20 95.00
V2S tl_intg_err flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
flash_ctrl_tl_intg_err 15.325m 1.340ms 19 20 95.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.325m 1.340ms 19 20 95.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.325m 1.340ms 19 20 95.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.620s 241.949us 3 3 100.00
flash_ctrl_wr_intg 14.560s 47.576us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 3.607m 37.124us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.248m 39.394us 80 80 100.00
flash_ctrl_disable 54.488m 120.022ms 45 50 90.00
flash_ctrl_sec_info_access 1.340m 2.726ms 50 50 100.00
flash_ctrl_connect 16.330s 20.941us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.190s 39.699us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 16.910s 66.665us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 15.730s 15.126us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 54.488m 120.022ms 45 50 90.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.620s 241.949us 3 3 100.00
flash_ctrl_access_after_disable 13.620s 37.392us 3 3 100.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 54.488m 120.022ms 45 50 90.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 29.790s 1.702ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 9.058m 6.362ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 8.977m 16.188ms 10 10 100.00
flash_ctrl_rw_derr 10.203m 15.941ms 10 10 100.00
flash_ctrl_integrity 10.342m 16.440ms 5 5 100.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 32.471m 552.004ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 19.380s 95.763us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.040s 24.263us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.500s 23.795us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.315h 1.061ms 5 5 100.00
V2S TOTAL 142 144 98.61
V3 asymmetric_read_path flash_ctrl_rd_ooo 44.350s 88.822us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1259 1278 98.51

Testplan Progress

Items Total Written Passing Progress
V1 9 9 6 66.67
V2 55 55 47 85.45
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.70 95.85 94.18 98.95 92.52 98.49 98.30 98.65

Failure Buckets

Past Results