FLASH_CTRL Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.607m	37.124us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.090s	14.599us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.820s	153.807us	4	5	80.00
V1	csr_rw	flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.214m	2.468ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.047m	1.236ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.220s	49.288us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
		flash_ctrl_csr_aliasing	1.047m	1.236ms	4	5	80.00
V1	mem_walk	flash_ctrl_mem_walk	13.310s	27.700us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.670s	15.974us	5	5	100.00
V1		TOTAL			117	120	97.50
V2	sw_op	flash_ctrl_sw_op	26.400s	205.947us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.533m	216.289us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.471m	552.004ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.407m	160.187ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.300s	16.095us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.801m	290.731ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.980m	4.429ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.157m	748.407us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	42.808m	325.454ms	2	5	40.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.225m	5.726ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	39.630s	2.258ms	39	40	97.50
		flash_ctrl_rw_evict_all_en	37.860s	483.406us	39	40	97.50
		flash_ctrl_re_evict	41.270s	153.735us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.314m	1.424ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.314m	1.424ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.045m	220.153ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.790s	1.702ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.564m	5.863ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.926m	8.822ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.817m	3.645ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.770m	2.087ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.610s	46.127us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.372m	3.040ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	54.488m	120.022ms	45	50	90.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.330s	20.941us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.299m	509.344us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.671m	11.567ms	50	50	100.00
		flash_ctrl_otp_reset	2.248m	39.394us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.471m	552.004ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	2.944m	19.899ms	40	40	100.00
		flash_ctrl_intr_wr	2.054m	28.547ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.749m	36.953ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	10.094m	72.768ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.492m	6.446ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.200m	3.277ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.730s	133.201us	5	5	100.00
		flash_ctrl_ro_derr	2.209m	2.768ms	10	10	100.00
		flash_ctrl_rw_derr	10.203m	15.941ms	10	10	100.00
		flash_ctrl_derr_detect	1.749m	113.670us	5	5	100.00
		flash_ctrl_integrity	10.342m	16.440ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.030s	176.604us	5	5	100.00
		flash_ctrl_ro_serr	2.220m	646.360us	10	10	100.00
		flash_ctrl_rw_serr	8.977m	16.188ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.358m	1.547ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.605m	3.753ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.341m	2.453ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.070s	238.278us	1	1	100.00
		flash_ctrl_read_word_sweep	13.940s	41.688us	1	1	100.00
		flash_ctrl_ro	2.008m	903.780us	20	20	100.00
		flash_ctrl_rw	9.058m	6.362ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.200s	1.136ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.136m	160.733ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.553m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.430s	166.110us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.280s	31.682us	49	50	98.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.210s	54.079us	19	20	95.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.210s	54.079us	19	20	95.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.820s	153.807us	4	5	80.00
		flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
		flash_ctrl_csr_aliasing	1.047m	1.236ms	4	5	80.00
		flash_ctrl_same_csr_outstanding	35.470s	199.263us	19	20	95.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.820s	153.807us	4	5	80.00
		flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
		flash_ctrl_csr_aliasing	1.047m	1.236ms	4	5	80.00
		flash_ctrl_same_csr_outstanding	35.470s	199.263us	19	20	95.00
V2		TOTAL			999	1013	98.62
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.730s	50.199us	19	20	95.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.325m	1.340ms	19	20	95.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.325m	1.340ms	19	20	95.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.325m	1.340ms	19	20	95.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.620s	241.949us	3	3	100.00
		flash_ctrl_wr_intg	14.560s	47.576us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.607m	37.124us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.248m	39.394us	80	80	100.00
		flash_ctrl_disable	54.488m	120.022ms	45	50	90.00
		flash_ctrl_sec_info_access	1.340m	2.726ms	50	50	100.00
		flash_ctrl_connect	16.330s	20.941us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.190s	39.699us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	16.910s	66.665us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.730s	15.126us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	54.488m	120.022ms	45	50	90.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.620s	241.949us	3	3	100.00
		flash_ctrl_access_after_disable	13.620s	37.392us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	54.488m	120.022ms	45	50	90.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.790s	1.702ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.058m	6.362ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	8.977m	16.188ms	10	10	100.00
		flash_ctrl_rw_derr	10.203m	15.941ms	10	10	100.00
		flash_ctrl_integrity	10.342m	16.440ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.471m	552.004ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.380s	95.763us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.040s	24.263us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.500s	23.795us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.315h	1.061ms	5	5	100.00
V2S		TOTAL			142	144	98.61
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.350s	88.822us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1278	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	6	66.67
V2	55	55	47	85.45
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	95.85	94.18	98.95	92.52	98.49	98.30	98.65

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 8 failures:

Test flash_ctrl_tl_intg_err has 1 failures.

0.flash_ctrl_tl_intg_err.109096203069814144729974613254449153386300393876564795490773202657227833593139
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log

  [make]: simulate
  cd /workspace/0.flash_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986252083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.1986252083
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 12:33 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test flash_ctrl_intr_test has 1 failures.

1.flash_ctrl_intr_test.29013600669095758725467677646755046074553871268683842582110659242838430184463
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest/run.log

  [make]: simulate
  cd /workspace/1.flash_ctrl_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094817295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.4094817295
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 12:34 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test flash_ctrl_csr_hw_reset has 1 failures.

1.flash_ctrl_csr_hw_reset.40248846038602072727262267058747120614926073167796816560466865586156894579695
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest/run.log

  [make]: simulate
  cd /workspace/1.flash_ctrl_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238709743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.238709743
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 12:34 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test flash_ctrl_csr_aliasing has 1 failures.

1.flash_ctrl_csr_aliasing.84469891738216313409386918124437585621382082642270332525289833432312393918752
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest/run.log

  [make]: simulate
  cd /workspace/1.flash_ctrl_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050044704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.1050044704
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 12:34 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test flash_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

1.flash_ctrl_csr_mem_rw_with_rand_reset.27239360574043748152242049478885077778438200803947261632106876166726611157900
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011115404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.4011115404
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 12:34 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

... and 3 more tests.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test flash_ctrl_full_mem_access has 3 failures.
  - 0.flash_ctrl_full_mem_access.73486332933413886500533430920616964012352862244442503422798939611632093466132
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:720fc155-7b1c-4832-8e36-a97b514d1a2c
```
  - 1.flash_ctrl_full_mem_access.1610839597149727402290338122576514261997183618988964678929078542786441910485
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:b0b1c154-c1d8-4b05-9ad6-d9f473715764
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=*) == * has 3 failures:
- Test flash_ctrl_disable has 3 failures.
  - 8.flash_ctrl_disable.77018425123549815172024842031315906907908934829467230668098959656111548614690
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 120126946.3 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0x40592d70) == 0x1
  UVM_INFO @ 120126946.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.flash_ctrl_disable.47095825130893518914109262638987545928620992736761793701603226216922934542732
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 120021874.7 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0xefd1f570) == 0x1
  UVM_INFO @ 120021874.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 13.flash_ctrl_rw_evict.63244829287561585559483828442341523629659086997197592524928565425595148443482
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 2258300.2 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 2258300.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 21.flash_ctrl_rw_evict_all_en.89227718971925684411136606488484812859545263542052848543276636308584813627636
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 58513.9 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 58513.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@82720) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

1.flash_ctrl_disable.79396256846112523251718342095281280356588961800374103741520208927056769821089
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 30200.3 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@82720) { a_addr: 'h9e7527b0  a_data: 'h976ab42d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he4  a_opcode: 'h1  a_user: 'h26f0a  d_param: 'h0  d_source: 'he4  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 30200.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 13.flash_ctrl_lcmgr_intg.75557032175746462049481856511945943650744556563618119422775088837812436271157
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 15636.3 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 15636.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=*) == * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 17.flash_ctrl_disable.77729371137410937348059730055941244642528825189499859900299080971984468819172
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 10007264.6 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0xd8b70974) == 0x1
  UVM_INFO @ 10007264.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```