Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336	1		T1	8		T2	8		T11	1
all_values[1]	336	1		T1	8		T2	8		T11	1
all_values[2]	336	1		T1	8		T2	8		T11	1
all_values[3]	336	1		T1	8		T2	8		T11	1
all_values[4]	336	1		T1	8		T2	8		T11	1
all_values[5]	336	1		T1	8		T2	8		T11	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1028	1		T1	23		T2	24		T11	6
auto[1]	988	1		T1	25		T2	24		T7	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	855	1		T1	18		T2	21		T11	4
auto[1]	1161	1		T1	30		T2	27		T11	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	180	1		T1	6		T2	6		T11	1
all_values[0]	auto[1]	auto[1]	156	1		T1	2		T2	2		T7	4
all_values[1]	auto[0]	auto[1]	172	1		T1	2		T2	7		T11	1
all_values[1]	auto[1]	auto[1]	164	1		T1	6		T2	1		T7	1
all_values[2]	auto[0]	auto[0]	116	1		T1	3		T2	1		T11	1
all_values[2]	auto[0]	auto[1]	53	1		T1	3		T2	1		T9	2
all_values[2]	auto[1]	auto[0]	118	1		T1	1		T2	5		T7	4
all_values[2]	auto[1]	auto[1]	49	1		T1	1		T2	1		T9	1
all_values[3]	auto[0]	auto[0]	109	1		T1	1		T11	1		T7	5
all_values[3]	auto[0]	auto[1]	61	1		T1	1		T2	2		T9	3
all_values[3]	auto[1]	auto[0]	93	1		T1	3		T2	3		T9	2
all_values[3]	auto[1]	auto[1]	73	1		T1	3		T2	3		T9	3
all_values[4]	auto[0]	auto[0]	110	1		T1	4		T2	3		T11	1
all_values[4]	auto[0]	auto[1]	56	1		T7	3		T9	1		T8	2
all_values[4]	auto[1]	auto[0]	98	1		T1	3		T2	3		T9	5
all_values[4]	auto[1]	auto[1]	72	1		T1	1		T2	2		T9	2
all_values[5]	auto[0]	auto[0]	108	1		T2	2		T11	1		T7	1
all_values[5]	auto[0]	auto[1]	63	1		T1	3		T2	2		T7	1
all_values[5]	auto[1]	auto[0]	103	1		T1	3		T2	4		T7	1
all_values[5]	auto[1]	auto[1]	62	1		T1	2		T7	2		T9	3