| | | | | | | | | | | |
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg |
0 |
31 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::erase_susp_cg |
0 |
1 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg |
0 |
42 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::hw_error_cg |
0 |
12 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg |
0 |
18 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg |
0 |
8 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg |
0 |
7 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg |
0 |
99 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg |
0 |
99 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg |
0 |
3 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg |
0 |
2 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg |
0 |
2 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg |
2 |
6 |
33.33 |
26.19 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg |
1 |
3 |
33.33 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg |
1 |
2 |
50.00 |
50.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::pending_req_on_rst_cg |
1 |
2 |
50.00 |
50.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg |
7 |
11 |
63.64 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5} |
40 |
48 |
83.33 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5} |
30 |
34 |
88.24 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
alert_esc_agent_pkg::alert_handshake_complete_cg |
3 |
3 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5} |
34 |
34 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg |
15 |
15 |
100.00 |
88.89 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg |
14 |
14 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg |
24 |
24 |
100.00 |
97.92 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg |
2 |
2 |
100.00 |
98.25 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg |
6 |
6 |
100.00 |
54.18 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg |
4 |
4 |
100.00 |
96.05 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
flash_ctrl_env_pkg::flash_ctrl_env_cov::rma_init_cg |
1 |
1 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} |
1 |
1 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=2} |
2 |
2 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} |
137 |
137 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|