Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
54.97 51.78 51.55 49.37 0.00 65.89 99.33 66.86


Total tests in report: 215
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.46 46.46 51.55 51.55 49.95 49.95 48.05 48.05 0.00 0.00 65.67 65.67 77.30 77.30 32.68 32.68 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4210026660
51.21 4.75 51.75 0.20 50.78 0.84 65.41 17.36 0.00 0.00 65.80 0.13 78.65 1.35 46.09 13.41 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1934457713
54.05 2.83 51.75 0.00 50.78 0.00 65.41 0.00 0.00 0.00 65.80 0.00 98.43 19.78 46.15 0.06 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4154228681
55.16 1.12 51.77 0.02 50.95 0.16 67.65 2.24 0.00 0.00 65.89 0.09 98.43 0.00 51.45 5.30 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2032003001
55.82 0.66 51.78 0.01 51.15 0.20 69.01 1.35 0.00 0.00 65.89 0.00 98.43 0.00 54.47 3.02 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3548947747
56.26 0.44 51.78 0.00 51.15 0.00 69.72 0.71 0.00 0.00 65.89 0.00 99.10 0.67 56.20 1.73 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3458964969
56.62 0.36 51.78 0.00 51.15 0.00 70.29 0.58 0.00 0.00 65.89 0.00 99.10 0.00 58.11 1.91 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2768962871
56.88 0.27 51.78 0.00 51.39 0.24 70.58 0.29 0.00 0.00 65.89 0.00 99.10 0.00 59.43 1.33 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2350477415
57.09 0.21 51.78 0.00 51.39 0.00 70.85 0.27 0.00 0.00 65.89 0.00 99.10 0.00 60.60 1.17 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2194467220
57.26 0.18 51.78 0.00 51.39 0.00 70.98 0.13 0.00 0.00 65.89 0.00 99.10 0.00 61.71 1.11 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3699372901
57.41 0.14 51.78 0.00 51.39 0.00 71.05 0.07 0.00 0.00 65.89 0.00 99.10 0.00 62.64 0.92 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.879102775
57.52 0.11 51.78 0.00 51.48 0.09 71.16 0.11 0.00 0.00 65.89 0.00 99.10 0.00 63.22 0.59 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.548793149
57.61 0.09 51.78 0.00 51.48 0.00 71.25 0.09 0.00 0.00 65.89 0.00 99.10 0.00 63.78 0.55 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3866174097
57.68 0.07 51.78 0.00 51.48 0.00 71.38 0.13 0.00 0.00 65.89 0.00 99.10 0.00 64.15 0.37 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2277301816
57.75 0.07 51.78 0.00 51.48 0.00 71.60 0.22 0.00 0.00 65.89 0.00 99.10 0.00 64.43 0.28 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2846479579
57.81 0.06 51.78 0.00 51.48 0.00 71.63 0.02 0.00 0.00 65.89 0.00 99.10 0.00 64.80 0.37 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.710050671
57.85 0.04 51.78 0.00 51.48 0.00 71.69 0.07 0.00 0.00 65.89 0.00 99.10 0.00 65.04 0.25 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1322093364
57.90 0.04 51.78 0.00 51.49 0.01 71.69 0.00 0.00 0.00 65.89 0.00 99.33 0.22 65.10 0.06 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.961507463
57.94 0.04 51.78 0.00 51.49 0.00 71.69 0.00 0.00 0.00 65.89 0.00 99.33 0.00 65.38 0.28 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2997993364
57.97 0.03 51.78 0.00 51.51 0.02 71.71 0.02 0.00 0.00 65.89 0.00 99.33 0.00 65.57 0.18 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3437164260
58.00 0.03 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 65.78 0.22 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.525551649
58.02 0.02 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 65.94 0.15 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1784407140
58.04 0.02 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.06 0.12 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.700146550
58.06 0.02 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.18 0.12 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2972809256
58.07 0.02 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.31 0.12 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3314671938
58.09 0.01 51.78 0.00 51.51 0.00 71.71 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.40 0.09 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.860201455
58.10 0.01 51.78 0.00 51.52 0.01 71.76 0.04 0.00 0.00 65.89 0.00 99.33 0.00 66.43 0.03 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1137941308
58.11 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.49 0.06 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.79694497
58.12 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.55 0.06 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3768379418
58.13 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.62 0.06 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2638908018
58.13 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.65 0.03 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2485199359
58.14 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.68 0.03 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4275253270
58.14 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.71 0.03 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2363296242
58.14 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.74 0.03 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.243627672
58.15 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.77 0.03 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4178220598
58.15 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.80 0.03 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1390377628
58.16 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.83 0.03 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1937645019
58.16 0.01 51.78 0.00 51.52 0.00 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.86 0.03 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1832379979
58.16 0.01 51.78 0.00 51.53 0.01 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.86 0.00 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2594904979
58.16 0.01 51.78 0.00 51.54 0.01 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.86 0.00 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3307181356
58.17 0.01 51.78 0.00 51.55 0.01 71.76 0.00 0.00 0.00 65.89 0.00 99.33 0.00 66.86 0.00 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1103983051

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3416730157
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.414837304
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3029228018
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4206932449
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.785791530
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.876624597
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.272685616
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3985829827
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.274113008
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4144412179
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1923452735
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.942181347
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3140136883
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2139600114
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2929305675
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.504779626
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3798548149
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3100082141
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.927518712
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2348119417
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2273548156
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2678252160
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3863053945
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1118028697
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1178499130
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3194027478
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3640136436
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1593158544
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1385332707
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1900723946
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1965120312
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3645461166
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.684016171
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2858872833
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2399776209
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2156760068
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3252967713
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.105961384
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.656456565
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3058992571
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3010035260
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2809189401
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2445732938
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.535240001
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1497526415
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3140596828
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.419439260
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.714007126
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3822517602
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3522688792
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2214143603
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.293535795
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.842359891
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.879363750
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.963284918
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3936338619
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3895797376
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.603583062
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3075101948
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.223240701
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3506660376
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4152567200
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.781644327
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2997524196
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2207877656
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3347967137
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.687215652
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2953670913
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1748544708
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1330401338
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1683077088
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.762868737
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1011903988
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1351010233
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3111555462
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2867851394
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2348120871
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4819181
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3423186674
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.676778849
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3777574623
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3409796430
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3882184502
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2093575563
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3409984973
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1554628923
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2321428160
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3288604326
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3433878906
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1889874938
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2675767268
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.589558729
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1233349755
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1757755071
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3124150670
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1662230504
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4179812069
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.769834939
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.779884940
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3786312151
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.846983740
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3975142794
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3861238298
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1516457541
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2905742416
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1415585490
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4264431530
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.290312107
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3248483148
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3825626560
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.960001671
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3924918211
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1145353624
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1283221657
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.57569396
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.885397512
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3361633350
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3472097620
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.579602938
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.212275340
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3068639716
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2878161715
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4178547806
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.733944091
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2018192259
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1231210149
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3568756560
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1152167399
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3009261662
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2643504207
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2148313078
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1250992330
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2929048599
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.169850004
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3869721276
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2156822751
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2262218061
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2455387562
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1947142872
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3334649809
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.432053898
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2820661115
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4157131459
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.444920652
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.336408365
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1347085543
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1132024966
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3327472085
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2502255118
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.872806514
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1112957004
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.146163647
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1258593845
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.75773331
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2721097870
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.129281402
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1850833295
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2708388515
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.223658311
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.105492196
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2357145258
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2037585302
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.353770463
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1473631368
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1232383417
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.364003046
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2083342047
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4122796529
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.136784807
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1896493670
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.498129113
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2650756060
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1454877076
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3236425968



Total test records in report: 215
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3327472085 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:06 PM PDT 24 24553900 ps
T2 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1516457541 Mar 14 12:27:14 PM PDT 24 Mar 14 12:27:28 PM PDT 24 14465800 ps
T3 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1233349755 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:09 PM PDT 24 66701200 ps
T13 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2708388515 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:05 PM PDT 24 69522900 ps
T11 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.79694497 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:56 PM PDT 24 55757900 ps
T4 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.769834939 Mar 14 12:26:47 PM PDT 24 Mar 14 12:34:24 PM PDT 24 2338345500 ps
T7 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2972809256 Mar 14 12:27:14 PM PDT 24 Mar 14 12:27:27 PM PDT 24 50363400 ps
T9 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2032003001 Mar 14 12:27:14 PM PDT 24 Mar 14 12:27:28 PM PDT 24 14948500 ps
T12 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2350477415 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:11 PM PDT 24 51196500 ps
T5 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4210026660 Mar 14 12:26:53 PM PDT 24 Mar 14 12:41:53 PM PDT 24 425851600 ps
T10 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.676778849 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:11 PM PDT 24 59705700 ps
T6 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1118028697 Mar 14 12:26:50 PM PDT 24 Mar 14 12:34:30 PM PDT 24 176616200 ps
T8 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.927518712 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:05 PM PDT 24 24551700 ps
T14 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1934457713 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:11 PM PDT 24 48056500 ps
T15 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3548947747 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:13 PM PDT 24 450381000 ps
T24 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1351010233 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:28 PM PDT 24 111505800 ps
T25 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1232383417 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:10 PM PDT 24 14181900 ps
T26 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2638908018 Mar 14 12:27:21 PM PDT 24 Mar 14 12:27:40 PM PDT 24 49977300 ps
T27 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1683077088 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:09 PM PDT 24 32556300 ps
T16 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1137941308 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:08 PM PDT 24 135767200 ps
T52 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2929305675 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:38 PM PDT 24 6784066600 ps
T83 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3861238298 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:26 PM PDT 24 26850000 ps
T84 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1937645019 Mar 14 12:27:35 PM PDT 24 Mar 14 12:27:49 PM PDT 24 14773300 ps
T127 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4819181 Mar 14 12:26:57 PM PDT 24 Mar 14 12:27:12 PM PDT 24 19096400 ps
T92 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3866174097 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:21 PM PDT 24 84682800 ps
T28 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.293535795 Mar 14 12:27:27 PM PDT 24 Mar 14 12:27:44 PM PDT 24 92329800 ps
T29 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.353770463 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:30 PM PDT 24 124342300 ps
T128 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2207877656 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:08 PM PDT 24 11302700 ps
T129 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.444920652 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:05 PM PDT 24 13984900 ps
T53 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3416730157 Mar 14 12:26:47 PM PDT 24 Mar 14 12:27:23 PM PDT 24 792236300 ps
T71 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.879363750 Mar 14 12:27:13 PM PDT 24 Mar 14 12:27:26 PM PDT 24 18574700 ps
T30 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.504779626 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:44 PM PDT 24 50906300 ps
T54 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3068639716 Mar 14 12:26:32 PM PDT 24 Mar 14 12:27:11 PM PDT 24 2135451500 ps
T72 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.876624597 Mar 14 12:26:50 PM PDT 24 Mar 14 12:27:05 PM PDT 24 250951500 ps
T73 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1390377628 Mar 14 12:26:48 PM PDT 24 Mar 14 12:27:02 PM PDT 24 51524900 ps
T49 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2273548156 Mar 14 12:26:47 PM PDT 24 Mar 14 12:27:06 PM PDT 24 1175458000 ps
T74 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1662230504 Mar 14 12:26:39 PM PDT 24 Mar 14 12:26:55 PM PDT 24 44389700 ps
T31 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4154228681 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:19 PM PDT 24 393146600 ps
T32 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.684016171 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:09 PM PDT 24 306312500 ps
T76 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2768962871 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:08 PM PDT 24 31418400 ps
T77 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4144412179 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:11 PM PDT 24 20696800 ps
T78 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.223240701 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:23 PM PDT 24 19068600 ps
T79 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1322093364 Mar 14 12:26:57 PM PDT 24 Mar 14 12:27:11 PM PDT 24 19261500 ps
T80 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.762868737 Mar 14 12:27:12 PM PDT 24 Mar 14 12:27:27 PM PDT 24 120100900 ps
T17 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2357145258 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:21 PM PDT 24 173167000 ps
T33 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2820661115 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:08 PM PDT 24 211404400 ps
T130 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1385332707 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:08 PM PDT 24 40284400 ps
T131 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2093575563 Mar 14 12:27:19 PM PDT 24 Mar 14 12:27:34 PM PDT 24 11594800 ps
T132 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3347967137 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:27 PM PDT 24 27590200 ps
T18 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.963284918 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:09 PM PDT 24 37799600 ps
T19 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4178547806 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:08 PM PDT 24 86737900 ps
T50 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2502255118 Mar 14 12:26:41 PM PDT 24 Mar 14 12:27:16 PM PDT 24 2561653200 ps
T93 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2277301816 Mar 14 12:27:15 PM PDT 24 Mar 14 12:27:29 PM PDT 24 15231400 ps
T133 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2139600114 Mar 14 12:26:33 PM PDT 24 Mar 14 12:27:35 PM PDT 24 1256375700 ps
T94 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2929048599 Mar 14 12:27:17 PM PDT 24 Mar 14 12:27:30 PM PDT 24 56478200 ps
T134 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1923452735 Mar 14 12:26:38 PM PDT 24 Mar 14 12:26:53 PM PDT 24 45831100 ps
T51 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1850833295 Mar 14 12:27:01 PM PDT 24 Mar 14 12:27:21 PM PDT 24 184185900 ps
T34 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3029228018 Mar 14 12:26:47 PM PDT 24 Mar 14 12:27:26 PM PDT 24 50358900 ps
T98 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1497526415 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:20 PM PDT 24 28841200 ps
T35 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.498129113 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:38 PM PDT 24 64565100 ps
T23 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2846479579 Mar 14 12:26:52 PM PDT 24 Mar 14 12:39:22 PM PDT 24 677972700 ps
T135 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.714007126 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:10 PM PDT 24 38938200 ps
T136 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3924918211 Mar 14 12:27:06 PM PDT 24 Mar 14 12:27:21 PM PDT 24 73604800 ps
T62 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3307181356 Mar 14 12:27:07 PM PDT 24 Mar 14 12:34:45 PM PDT 24 1441576800 ps
T69 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2214143603 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:21 PM PDT 24 127979600 ps
T137 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1473631368 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:19 PM PDT 24 36812500 ps
T20 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.75773331 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:08 PM PDT 24 90600500 ps
T36 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.785791530 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:06 PM PDT 24 306541800 ps
T102 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2997993364 Mar 14 12:27:06 PM PDT 24 Mar 14 12:27:19 PM PDT 24 69755500 ps
T96 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3699372901 Mar 14 12:27:12 PM PDT 24 Mar 14 12:27:25 PM PDT 24 29117500 ps
T65 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.687215652 Mar 14 12:27:03 PM PDT 24 Mar 14 12:33:29 PM PDT 24 1584618100 ps
T21 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3458964969 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:03 PM PDT 24 30427500 ps
T22 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.336408365 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:12 PM PDT 24 52351500 ps
T37 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.733944091 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:55 PM PDT 24 39846300 ps
T38 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3433878906 Mar 14 12:26:46 PM PDT 24 Mar 14 12:27:18 PM PDT 24 54448100 ps
T39 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1112957004 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:56 PM PDT 24 14013200 ps
T40 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3777574623 Mar 14 12:27:09 PM PDT 24 Mar 14 12:27:23 PM PDT 24 79784800 ps
T41 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3409796430 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:13 PM PDT 24 34762100 ps
T42 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4275253270 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:25 PM PDT 24 27357900 ps
T43 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3314671938 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:06 PM PDT 24 17824900 ps
T44 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2194467220 Mar 14 12:27:00 PM PDT 24 Mar 14 12:27:14 PM PDT 24 51535900 ps
T138 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2399776209 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:20 PM PDT 24 15097100 ps
T85 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4179812069 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:47 PM PDT 24 131940800 ps
T106 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3472097620 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:23 PM PDT 24 28812000 ps
T95 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3869721276 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:23 PM PDT 24 57903900 ps
T139 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3288604326 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:54 PM PDT 24 663916700 ps
T100 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.879102775 Mar 14 12:26:48 PM PDT 24 Mar 14 12:27:01 PM PDT 24 29843500 ps
T140 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3010035260 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:26 PM PDT 24 46793700 ps
T63 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2643504207 Mar 14 12:26:47 PM PDT 24 Mar 14 12:27:03 PM PDT 24 176820000 ps
T141 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3124150670 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:05 PM PDT 24 102021700 ps
T66 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2594904979 Mar 14 12:27:07 PM PDT 24 Mar 14 12:39:37 PM PDT 24 2606768200 ps
T70 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.57569396 Mar 14 12:26:50 PM PDT 24 Mar 14 12:34:32 PM PDT 24 949044400 ps
T105 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.781644327 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:07 PM PDT 24 29834500 ps
T142 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1900723946 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:08 PM PDT 24 15712400 ps
T143 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.872806514 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:10 PM PDT 24 13538900 ps
T57 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1103983051 Mar 14 12:26:51 PM PDT 24 Mar 14 12:33:14 PM PDT 24 1550620600 ps
T75 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3936338619 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:28 PM PDT 24 483956600 ps
T118 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1896493670 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:06 PM PDT 24 17126600 ps
T144 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1454877076 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:13 PM PDT 24 13513400 ps
T59 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3437164260 Mar 14 12:27:19 PM PDT 24 Mar 14 12:27:37 PM PDT 24 88785600 ps
T45 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.710050671 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:04 PM PDT 24 31631300 ps
T61 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.961507463 Mar 14 12:26:51 PM PDT 24 Mar 14 12:34:28 PM PDT 24 1700355800 ps
T108 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3111555462 Mar 14 12:27:16 PM PDT 24 Mar 14 12:27:30 PM PDT 24 14735000 ps
T55 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.548793149 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:11 PM PDT 24 168697100 ps
T145 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1593158544 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:07 PM PDT 24 278188600 ps
T101 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1231210149 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:03 PM PDT 24 45751900 ps
T81 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.212275340 Mar 14 12:26:40 PM PDT 24 Mar 14 12:27:42 PM PDT 24 1624824900 ps
T146 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.842359891 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:24 PM PDT 24 18395700 ps
T116 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3248483148 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:05 PM PDT 24 17000400 ps
T111 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.432053898 Mar 14 12:26:50 PM PDT 24 Mar 14 12:27:03 PM PDT 24 55637300 ps
T56 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3409984973 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:10 PM PDT 24 123010100 ps
T147 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.105961384 Mar 14 12:27:12 PM PDT 24 Mar 14 12:27:26 PM PDT 24 34344500 ps
T148 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2348120871 Mar 14 12:27:16 PM PDT 24 Mar 14 12:27:32 PM PDT 24 13773000 ps
T97 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2262218061 Mar 14 12:27:09 PM PDT 24 Mar 14 12:27:22 PM PDT 24 47060600 ps
T149 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4157131459 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:12 PM PDT 24 24377300 ps
T88 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1832379979 Mar 14 12:27:07 PM PDT 24 Mar 14 12:42:23 PM PDT 24 2608384300 ps
T150 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1330401338 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:15 PM PDT 24 801835700 ps
T58 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3768379418 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:30 PM PDT 24 200345200 ps
T151 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1965120312 Mar 14 12:27:14 PM PDT 24 Mar 14 12:27:29 PM PDT 24 73599900 ps
T152 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1415585490 Mar 14 12:27:05 PM PDT 24 Mar 14 12:28:31 PM PDT 24 9087079700 ps
T104 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.579602938 Mar 14 12:27:15 PM PDT 24 Mar 14 12:27:29 PM PDT 24 57305500 ps
T68 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4178220598 Mar 14 12:27:08 PM PDT 24 Mar 14 12:39:43 PM PDT 24 836215900 ps
T153 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3568756560 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:27 PM PDT 24 646249200 ps
T154 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3645461166 Mar 14 12:27:08 PM PDT 24 Mar 14 12:27:25 PM PDT 24 48368100 ps
T155 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2675767268 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:09 PM PDT 24 635125300 ps
T156 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3140596828 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:22 PM PDT 24 37776300 ps
T157 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2721097870 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:12 PM PDT 24 90289100 ps
T158 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3863053945 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:57 PM PDT 24 42242500 ps
T89 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1258593845 Mar 14 12:26:44 PM PDT 24 Mar 14 12:34:25 PM PDT 24 457318000 ps
T159 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2878161715 Mar 14 12:26:47 PM PDT 24 Mar 14 12:27:33 PM PDT 24 46778800 ps
T46 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.272685616 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:16 PM PDT 24 55537800 ps
T91 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3140136883 Mar 14 12:26:50 PM PDT 24 Mar 14 12:41:39 PM PDT 24 1801995900 ps
T160 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1152167399 Mar 14 12:26:50 PM PDT 24 Mar 14 12:27:03 PM PDT 24 41279200 ps
T161 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1947142872 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:21 PM PDT 24 403928900 ps
T90 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.860201455 Mar 14 12:26:54 PM PDT 24 Mar 14 12:39:30 PM PDT 24 2099962600 ps
T112 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3786312151 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:09 PM PDT 24 26738500 ps
T103 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1748544708 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:03 PM PDT 24 95774800 ps
T126 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1178499130 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:14 PM PDT 24 41550600 ps
T114 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3895797376 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:07 PM PDT 24 30060000 ps
T162 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2867851394 Mar 14 12:26:56 PM PDT 24 Mar 14 12:27:15 PM PDT 24 175751700 ps
T163 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2321428160 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:44 PM PDT 24 1712448100 ps
T164 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2083342047 Mar 14 12:27:06 PM PDT 24 Mar 14 12:34:45 PM PDT 24 753374500 ps
T165 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3361633350 Mar 14 12:27:13 PM PDT 24 Mar 14 12:27:27 PM PDT 24 54066900 ps
T166 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1554628923 Mar 14 12:27:09 PM PDT 24 Mar 14 12:34:58 PM PDT 24 2279107600 ps
T107 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1250992330 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:23 PM PDT 24 15072700 ps
T167 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.419439260 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:07 PM PDT 24 41190100 ps
T60 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.942181347 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:08 PM PDT 24 102772500 ps
T168 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3058992571 Mar 14 12:27:16 PM PDT 24 Mar 14 12:27:29 PM PDT 24 16830100 ps
T169 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1145353624 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:07 PM PDT 24 25355600 ps
T82 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.960001671 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:24 PM PDT 24 1527916400 ps
T170 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.274113008 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:07 PM PDT 24 123231500 ps
T171 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4152567200 Mar 14 12:27:06 PM PDT 24 Mar 14 12:27:20 PM PDT 24 48732400 ps
T172 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1757755071 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:22 PM PDT 24 36789500 ps
T173 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2997524196 Mar 14 12:27:13 PM PDT 24 Mar 14 12:27:31 PM PDT 24 192711300 ps
T174 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2445732938 Mar 14 12:27:23 PM PDT 24 Mar 14 12:27:41 PM PDT 24 39113100 ps
T175 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1011903988 Mar 14 12:27:13 PM PDT 24 Mar 14 12:27:32 PM PDT 24 651942500 ps
T123 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2455387562 Mar 14 12:27:13 PM PDT 24 Mar 14 12:27:26 PM PDT 24 46086000 ps
T176 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.656456565 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:40 PM PDT 24 60893700 ps
T115 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2018192259 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:05 PM PDT 24 48339400 ps
T177 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3506660376 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:09 PM PDT 24 362078800 ps
T178 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2148313078 Mar 14 12:26:51 PM PDT 24 Mar 14 12:34:26 PM PDT 24 673186700 ps
T179 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3334649809 Mar 14 12:26:40 PM PDT 24 Mar 14 12:26:56 PM PDT 24 146200500 ps
T180 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4122796529 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:28 PM PDT 24 320860600 ps
T181 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2905742416 Mar 14 12:26:45 PM PDT 24 Mar 14 12:27:36 PM PDT 24 448387300 ps
T182 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1784407140 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:21 PM PDT 24 90086300 ps
T183 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2037585302 Mar 14 12:27:08 PM PDT 24 Mar 14 12:27:25 PM PDT 24 163793900 ps
T184 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3009261662 Mar 14 12:26:35 PM PDT 24 Mar 14 12:26:52 PM PDT 24 37046000 ps
T185 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.535240001 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:12 PM PDT 24 24304300 ps
T113 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.589558729 Mar 14 12:26:40 PM PDT 24 Mar 14 12:26:54 PM PDT 24 17032100 ps
T86 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2485199359 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:26 PM PDT 24 92111800 ps
T122 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2363296242 Mar 14 12:27:12 PM PDT 24 Mar 14 12:27:25 PM PDT 24 18128200 ps
T186 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1347085543 Mar 14 12:26:27 PM PDT 24 Mar 14 12:26:45 PM PDT 24 81669400 ps
T125 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.885397512 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:11 PM PDT 24 18320100 ps
T99 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.700146550 Mar 14 12:27:09 PM PDT 24 Mar 14 12:27:27 PM PDT 24 36394000 ps
T187 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3822517602 Mar 14 12:27:21 PM PDT 24 Mar 14 12:42:32 PM PDT 24 356719300 ps
T47 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3825626560 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:05 PM PDT 24 33665600 ps
T188 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3075101948 Mar 14 12:27:26 PM PDT 24 Mar 14 12:27:40 PM PDT 24 43236400 ps
T121 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3975142794 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:06 PM PDT 24 17080600 ps
T64 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3236425968 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:13 PM PDT 24 52014200 ps
T120 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.525551649 Mar 14 12:27:32 PM PDT 24 Mar 14 12:27:46 PM PDT 24 29900800 ps
T48 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2348119417 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:08 PM PDT 24 16643400 ps
T189 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2156760068 Mar 14 12:27:09 PM PDT 24 Mar 14 12:34:53 PM PDT 24 706004100 ps
T67 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1283221657 Mar 14 12:26:48 PM PDT 24 Mar 14 12:27:07 PM PDT 24 105402100 ps
T190 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.243627672 Mar 14 12:26:57 PM PDT 24 Mar 14 12:27:13 PM PDT 24 156176800 ps
T191 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3522688792 Mar 14 12:27:21 PM PDT 24 Mar 14 12:27:40 PM PDT 24 73883700 ps
T192 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.223658311 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:11 PM PDT 24 44942400 ps
T117 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.779884940 Mar 14 12:27:06 PM PDT 24 Mar 14 12:27:19 PM PDT 24 55902100 ps
T193 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4206932449 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:08 PM PDT 24 330072700 ps
T194 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1889874938 Mar 14 12:26:59 PM PDT 24 Mar 14 12:27:16 PM PDT 24 48766200 ps
T195 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.364003046 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:11 PM PDT 24 98578700 ps
T196 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2650756060 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:21 PM PDT 24 33170900 ps
T197 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3100082141 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:20 PM PDT 24 52166700 ps
T198 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3194027478 Mar 14 12:27:00 PM PDT 24 Mar 14 12:27:16 PM PDT 24 91623700 ps
T199 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4264431530 Mar 14 12:26:49 PM PDT 24 Mar 14 12:27:20 PM PDT 24 108429700 ps
T109 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3640136436 Mar 14 12:26:58 PM PDT 24 Mar 14 12:27:12 PM PDT 24 53204700 ps
T110 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3985829827 Mar 14 12:26:40 PM PDT 24 Mar 14 12:26:53 PM PDT 24 21852600 ps
T124 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.169850004 Mar 14 12:27:37 PM PDT 24 Mar 14 12:27:51 PM PDT 24 16749500 ps
T200 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1132024966 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:27 PM PDT 24 191642800 ps
T201 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3882184502 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:09 PM PDT 24 19284600 ps
T202 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.290312107 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:09 PM PDT 24 84664300 ps
T203 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2678252160 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:17 PM PDT 24 44531900 ps
T204 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.414837304 Mar 14 12:26:52 PM PDT 24 Mar 14 12:27:30 PM PDT 24 655740900 ps
T87 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2809189401 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:24 PM PDT 24 106931100 ps
T119 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.105492196 Mar 14 12:26:51 PM PDT 24 Mar 14 12:27:09 PM PDT 24 87210700 ps
T205 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.146163647 Mar 14 12:26:28 PM PDT 24 Mar 14 12:26:46 PM PDT 24 81612400 ps
T206 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.136784807 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:11 PM PDT 24 45740900 ps
T207 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.129281402 Mar 14 12:26:50 PM PDT 24 Mar 14 12:27:03 PM PDT 24 41003800 ps
T208 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3798548149 Mar 14 12:26:43 PM PDT 24 Mar 14 12:27:01 PM PDT 24 28692700 ps
T209 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.846983740 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:08 PM PDT 24 48597200 ps
T210 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.603583062 Mar 14 12:27:07 PM PDT 24 Mar 14 12:27:37 PM PDT 24 313788600 ps
T211 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2953670913 Mar 14 12:27:10 PM PDT 24 Mar 14 12:27:26 PM PDT 24 74187100 ps
T212 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3252967713 Mar 14 12:27:20 PM PDT 24 Mar 14 12:27:40 PM PDT 24 155323100 ps
T213 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2858872833 Mar 14 12:26:55 PM PDT 24 Mar 14 12:27:11 PM PDT 24 13498600 ps
T214 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2156822751 Mar 14 12:26:53 PM PDT 24 Mar 14 12:27:07 PM PDT 24 16942500 ps
T215 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3423186674 Mar 14 12:26:54 PM PDT 24 Mar 14 12:27:13 PM PDT 24 431850300 ps

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4210026660
Short name T5
Test name
Test status
Simulation time 425851600 ps
CPU time 899.75 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:41:53 PM PDT 24
Peak memory 263948 kb
Host smart-25fa13dc-00b5-4135-8364-889b78cf1d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210026660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.4210026660
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1934457713
Short name T14
Test name
Test status
Simulation time 48056500 ps
CPU time 18.03 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 263924 kb
Host smart-e0a0b3f1-7f34-4aab-ba9e-cbff6846e1a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934457713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
1934457713
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4154228681
Short name T31
Test name
Test status
Simulation time 393146600 ps
CPU time 17.31 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 260148 kb
Host smart-15fc70a4-682b-4bfe-9f77-3fbb09aaab05
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154228681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.4154228681
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2032003001
Short name T9
Test name
Test status
Simulation time 14948500 ps
CPU time 13.24 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 262376 kb
Host smart-e1794f30-7580-4d34-8d57-a7c8b7330aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032003001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2032003001
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3548947747
Short name T15
Test name
Test status
Simulation time 450381000 ps
CPU time 18.93 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 261020 kb
Host smart-dc3ce8ed-ae6b-4aed-9811-e7908908dc38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548947747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
3548947747
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3458964969
Short name T21
Test name
Test status
Simulation time 30427500 ps
CPU time 13.33 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 263664 kb
Host smart-9c19479f-4968-47ce-a2e4-7b48647488fe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458964969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.3458964969
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2768962871
Short name T76
Test name
Test status
Simulation time 31418400 ps
CPU time 13.24 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 262308 kb
Host smart-193ed457-b323-49d9-9413-eb44999874cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768962871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2768962871
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2350477415
Short name T12
Test name
Test status
Simulation time 51196500 ps
CPU time 18.02 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 263848 kb
Host smart-4563db87-aab2-4eba-9b55-ae4e644d4e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350477415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2350477415
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2194467220
Short name T44
Test name
Test status
Simulation time 51535900 ps
CPU time 13.54 seconds
Started Mar 14 12:27:00 PM PDT 24
Finished Mar 14 12:27:14 PM PDT 24
Peak memory 262240 kb
Host smart-6583850f-87ea-4cec-8caa-53be16e2d175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194467220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
194467220
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3699372901
Short name T96
Test name
Test status
Simulation time 29117500 ps
CPU time 13.28 seconds
Started Mar 14 12:27:12 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 262252 kb
Host smart-830b4c57-8278-48ce-9165-a881c0b5b2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699372901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3699372901
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.879102775
Short name T100
Test name
Test status
Simulation time 29843500 ps
CPU time 13.18 seconds
Started Mar 14 12:26:48 PM PDT 24
Finished Mar 14 12:27:01 PM PDT 24
Peak memory 262464 kb
Host smart-2658d204-1405-4ba2-bac1-489cfe486c72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879102775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.879102775
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.548793149
Short name T55
Test name
Test status
Simulation time 168697100 ps
CPU time 17.8 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 263940 kb
Host smart-2d7274bd-005e-4a02-b20a-5ea6ae91ab06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548793149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.548793149
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3866174097
Short name T92
Test name
Test status
Simulation time 84682800 ps
CPU time 13.33 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 262592 kb
Host smart-ef87d65e-475e-441a-9983-ccef7dea63cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866174097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3866174097
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2277301816
Short name T93
Test name
Test status
Simulation time 15231400 ps
CPU time 13.45 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:29 PM PDT 24
Peak memory 261532 kb
Host smart-2615bdb6-7c52-4832-b47f-cafdb8f1a3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277301816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2277301816
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2846479579
Short name T23
Test name
Test status
Simulation time 677972700 ps
CPU time 749.44 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:39:22 PM PDT 24
Peak memory 263892 kb
Host smart-f47d25dd-ecb0-4545-9fb8-95311ad4ca47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846479579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.2846479579
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.710050671
Short name T45
Test name
Test status
Simulation time 31631300 ps
CPU time 13.53 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:04 PM PDT 24
Peak memory 263432 kb
Host smart-e1640519-3466-40cf-b158-863ed2a7db7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710050671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.710050671
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1322093364
Short name T79
Test name
Test status
Simulation time 19261500 ps
CPU time 13.31 seconds
Started Mar 14 12:26:57 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 262540 kb
Host smart-50e935a9-8a89-4029-9751-26024d21f6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322093364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1322093364
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.961507463
Short name T61
Test name
Test status
Simulation time 1700355800 ps
CPU time 456.57 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:34:28 PM PDT 24
Peak memory 260100 kb
Host smart-9e81c0e4-2684-473f-84a8-60b9738b6383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961507463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
tl_intg_err.961507463
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2997993364
Short name T102
Test name
Test status
Simulation time 69755500 ps
CPU time 13.43 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 262432 kb
Host smart-5baa786d-d522-4f58-aa63-76c5ef0c9945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997993364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2997993364
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3437164260
Short name T59
Test name
Test status
Simulation time 88785600 ps
CPU time 17.99 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:37 PM PDT 24
Peak memory 263916 kb
Host smart-d79b3f45-d042-4a71-b101-ac392d7ab400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437164260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3437164260
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.525551649
Short name T120
Test name
Test status
Simulation time 29900800 ps
CPU time 13.41 seconds
Started Mar 14 12:27:32 PM PDT 24
Finished Mar 14 12:27:46 PM PDT 24
Peak memory 262436 kb
Host smart-aa3db39b-1381-43c9-b4f2-418fa67e78c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525551649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.525551649
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1784407140
Short name T182
Test name
Test status
Simulation time 90086300 ps
CPU time 13.39 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 262372 kb
Host smart-44329e0d-c5e7-427e-bba8-d4c28eb2727c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784407140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1784407140
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.700146550
Short name T99
Test name
Test status
Simulation time 36394000 ps
CPU time 13.33 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 262600 kb
Host smart-59f35620-fe6e-47ec-9fe9-3d8d3b65c55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700146550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.700146550
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2972809256
Short name T7
Test name
Test status
Simulation time 50363400 ps
CPU time 13.35 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 262572 kb
Host smart-16898dc7-ef38-427d-987c-f450fd91d7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972809256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2972809256
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3314671938
Short name T43
Test name
Test status
Simulation time 17824900 ps
CPU time 13.71 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 262360 kb
Host smart-a4e8201b-b75c-4c77-b003-8927a77bbbb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314671938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
3314671938
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.860201455
Short name T90
Test name
Test status
Simulation time 2099962600 ps
CPU time 755.57 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:39:30 PM PDT 24
Peak memory 263884 kb
Host smart-bf35f17b-ef32-4a08-8a6d-a2cda66114ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860201455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.860201455
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1137941308
Short name T16
Test name
Test status
Simulation time 135767200 ps
CPU time 14.81 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 276260 kb
Host smart-0f6ce140-30a1-418a-8356-629b23275cee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137941308 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1137941308
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.79694497
Short name T11
Test name
Test status
Simulation time 55757900 ps
CPU time 15.52 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 263900 kb
Host smart-1253f1a7-7830-4126-a2c8-c153dcd4cbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79694497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.79694497
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3768379418
Short name T58
Test name
Test status
Simulation time 200345200 ps
CPU time 18.99 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 263880 kb
Host smart-5b98e08f-70ce-41c0-a69f-54f1b6519d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768379418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3768379418
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2638908018
Short name T26
Test name
Test status
Simulation time 49977300 ps
CPU time 13.66 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 262276 kb
Host smart-f25dc3db-4dae-44cd-8744-a876be350f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638908018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2638908018
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2485199359
Short name T86
Test name
Test status
Simulation time 92111800 ps
CPU time 15.99 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 263884 kb
Host smart-998cef8c-f91f-43cf-b7b5-c568d19263eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485199359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2485199359
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4275253270
Short name T42
Test name
Test status
Simulation time 27357900 ps
CPU time 13.37 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 262356 kb
Host smart-6aac7663-be1e-44e8-99e7-b330ce28c49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275253270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
4275253270
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2363296242
Short name T122
Test name
Test status
Simulation time 18128200 ps
CPU time 13.29 seconds
Started Mar 14 12:27:12 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 262120 kb
Host smart-92651b7c-673a-4864-ab45-47d084d91dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363296242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2363296242
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.243627672
Short name T190
Test name
Test status
Simulation time 156176800 ps
CPU time 15.62 seconds
Started Mar 14 12:26:57 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 263976 kb
Host smart-e7c70e4f-e841-4d54-b4c0-743d347a2580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243627672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.243627672
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4178220598
Short name T68
Test name
Test status
Simulation time 836215900 ps
CPU time 755.11 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:39:43 PM PDT 24
Peak memory 263820 kb
Host smart-843ef43b-ff96-47a8-a858-f1480f6a8bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178220598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.4178220598
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1390377628
Short name T73
Test name
Test status
Simulation time 51524900 ps
CPU time 13.45 seconds
Started Mar 14 12:26:48 PM PDT 24
Finished Mar 14 12:27:02 PM PDT 24
Peak memory 262520 kb
Host smart-43fc7872-db38-4e14-b66c-4203ed116b62
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390377628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1390377628
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1937645019
Short name T84
Test name
Test status
Simulation time 14773300 ps
CPU time 13.76 seconds
Started Mar 14 12:27:35 PM PDT 24
Finished Mar 14 12:27:49 PM PDT 24
Peak memory 262324 kb
Host smart-9f331a1b-d6e2-490a-9fe2-2f77e5d14099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937645019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1937645019
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1832379979
Short name T88
Test name
Test status
Simulation time 2608384300 ps
CPU time 915.67 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:42:23 PM PDT 24
Peak memory 260384 kb
Host smart-b5f6586d-216a-4444-8ff4-75a2c608899f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832379979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1832379979
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2594904979
Short name T66
Test name
Test status
Simulation time 2606768200 ps
CPU time 750.05 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:39:37 PM PDT 24
Peak memory 262744 kb
Host smart-bd2262fd-1be2-4cd3-83a9-84249b0c4c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594904979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2594904979
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3307181356
Short name T62
Test name
Test status
Simulation time 1441576800 ps
CPU time 457.7 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 263800 kb
Host smart-bf8e6fc7-6e53-47c7-9774-5003d92de562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307181356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3307181356
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1103983051
Short name T57
Test name
Test status
Simulation time 1550620600 ps
CPU time 383.64 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:33:14 PM PDT 24
Peak memory 263892 kb
Host smart-3ac409fd-dc48-47cb-90c1-b572df3984c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103983051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.1103983051
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3416730157
Short name T53
Test name
Test status
Simulation time 792236300 ps
CPU time 35.43 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 260108 kb
Host smart-f174e081-6fae-458a-b477-b8fa2a8c1451
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416730157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.3416730157
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.414837304
Short name T204
Test name
Test status
Simulation time 655740900 ps
CPU time 37.43 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 262764 kb
Host smart-dc042ac6-874e-44e1-aa0e-44a2fdb42791
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414837304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.414837304
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3029228018
Short name T34
Test name
Test status
Simulation time 50358900 ps
CPU time 38.36 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 260220 kb
Host smart-7d298e73-ad56-4bec-89c1-c33d7538798d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029228018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.3029228018
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4206932449
Short name T193
Test name
Test status
Simulation time 330072700 ps
CPU time 15.79 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 272068 kb
Host smart-c9942b45-1efc-4420-83fe-1d69427f8eb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206932449 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.4206932449
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.785791530
Short name T36
Test name
Test status
Simulation time 306541800 ps
CPU time 16.8 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 260068 kb
Host smart-467be39e-c737-4356-a11c-d730d7e0d94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785791530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_csr_rw.785791530
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.876624597
Short name T72
Test name
Test status
Simulation time 250951500 ps
CPU time 13.74 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 262264 kb
Host smart-b826dadf-83b9-4550-99ec-0fd50244a205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876624597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.876624597
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.272685616
Short name T46
Test name
Test status
Simulation time 55537800 ps
CPU time 13.51 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 260748 kb
Host smart-435f1b59-295b-47dd-9536-1fc23bc858ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272685616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.272685616
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3985829827
Short name T110
Test name
Test status
Simulation time 21852600 ps
CPU time 13.26 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 262500 kb
Host smart-0a908fc1-d59e-4f11-8131-4ff37ca2f0e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985829827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3985829827
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.274113008
Short name T170
Test name
Test status
Simulation time 123231500 ps
CPU time 17.04 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 260312 kb
Host smart-9af649a6-3bb7-4a34-835e-f973abd34557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274113008 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.274113008
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4144412179
Short name T77
Test name
Test status
Simulation time 20696800 ps
CPU time 15.52 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 260184 kb
Host smart-71ec574f-be17-4661-a564-a01123807748
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144412179 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.4144412179
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1923452735
Short name T134
Test name
Test status
Simulation time 45831100 ps
CPU time 15.18 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 260268 kb
Host smart-d9decdab-1ee6-45ed-ae70-03737b928892
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923452735 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.1923452735
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.942181347
Short name T60
Test name
Test status
Simulation time 102772500 ps
CPU time 16.48 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 263876 kb
Host smart-380af600-bc3f-49d9-b139-2686b3d31f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942181347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.942181347
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3140136883
Short name T91
Test name
Test status
Simulation time 1801995900 ps
CPU time 889.59 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:41:39 PM PDT 24
Peak memory 263872 kb
Host smart-9c01e2b0-18aa-4740-ab7b-0eeda47a4a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140136883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.3140136883
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2139600114
Short name T133
Test name
Test status
Simulation time 1256375700 ps
CPU time 61.01 seconds
Started Mar 14 12:26:33 PM PDT 24
Finished Mar 14 12:27:35 PM PDT 24
Peak memory 260096 kb
Host smart-ca06178f-6d28-4f7e-b0ff-7570f4efbb0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139600114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2139600114
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2929305675
Short name T52
Test name
Test status
Simulation time 6784066600 ps
CPU time 48.33 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 260068 kb
Host smart-1cf0b6ce-18fb-4230-9d12-63ac9c4f6192
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929305675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.2929305675
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.504779626
Short name T30
Test name
Test status
Simulation time 50906300 ps
CPU time 38.54 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 260156 kb
Host smart-f4d1f91b-3899-4806-9add-f09dd3926134
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504779626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.504779626
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3798548149
Short name T208
Test name
Test status
Simulation time 28692700 ps
CPU time 18.01 seconds
Started Mar 14 12:26:43 PM PDT 24
Finished Mar 14 12:27:01 PM PDT 24
Peak memory 277708 kb
Host smart-ee5c8908-8015-4237-82ab-bd8f037304e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798548149 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3798548149
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3100082141
Short name T197
Test name
Test status
Simulation time 52166700 ps
CPU time 16.82 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 260352 kb
Host smart-7420ed17-ea74-4c08-a498-dd6b4b0a0e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100082141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3100082141
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.927518712
Short name T8
Test name
Test status
Simulation time 24551700 ps
CPU time 13.13 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 262456 kb
Host smart-8fac97d9-d3e6-4e3c-b2b7-28b116287aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927518712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.927518712
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2348119417
Short name T48
Test name
Test status
Simulation time 16643400 ps
CPU time 13.44 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 263644 kb
Host smart-3e62707e-3917-4b5f-9969-22c9a2833115
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348119417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2348119417
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2273548156
Short name T49
Test name
Test status
Simulation time 1175458000 ps
CPU time 19.32 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 261900 kb
Host smart-ff687c9e-e6d8-4722-bfdc-6481b274bcf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273548156 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2273548156
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2678252160
Short name T203
Test name
Test status
Simulation time 44531900 ps
CPU time 13.05 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:17 PM PDT 24
Peak memory 260136 kb
Host smart-ba4607c0-f594-4641-b309-2b3d341617a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678252160 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2678252160
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3863053945
Short name T158
Test name
Test status
Simulation time 42242500 ps
CPU time 15.72 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:57 PM PDT 24
Peak memory 260040 kb
Host smart-ce198789-232c-4271-baaa-b805005ff966
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863053945 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3863053945
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1118028697
Short name T6
Test name
Test status
Simulation time 176616200 ps
CPU time 459.98 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:34:30 PM PDT 24
Peak memory 260252 kb
Host smart-5bbe7cc1-1cb6-42d9-aee7-8df93bfebf41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118028697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1118028697
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1178499130
Short name T126
Test name
Test status
Simulation time 41550600 ps
CPU time 19.14 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:14 PM PDT 24
Peak memory 271992 kb
Host smart-9946729f-66b9-4db3-a5f5-e1c979912b4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178499130 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1178499130
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3194027478
Short name T198
Test name
Test status
Simulation time 91623700 ps
CPU time 16.55 seconds
Started Mar 14 12:27:00 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 260052 kb
Host smart-68fa1b96-daac-4de2-a9ea-df00460a41e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194027478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.3194027478
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3640136436
Short name T109
Test name
Test status
Simulation time 53204700 ps
CPU time 13.59 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 262544 kb
Host smart-cbfb5bee-e1c8-4c30-a4d5-93638379f35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640136436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
3640136436
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1593158544
Short name T145
Test name
Test status
Simulation time 278188600 ps
CPU time 17.23 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 260252 kb
Host smart-05dba736-43b5-4a25-a4c0-a04daeaebae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593158544 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1593158544
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1385332707
Short name T130
Test name
Test status
Simulation time 40284400 ps
CPU time 16.08 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 260060 kb
Host smart-a1ece5d2-8bbd-4b73-9499-1554fb45b818
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385332707 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1385332707
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1900723946
Short name T142
Test name
Test status
Simulation time 15712400 ps
CPU time 12.84 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 260180 kb
Host smart-92df8f68-f35a-40dc-8767-fc1509601614
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900723946 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1900723946
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1965120312
Short name T151
Test name
Test status
Simulation time 73599900 ps
CPU time 15.57 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:29 PM PDT 24
Peak memory 272036 kb
Host smart-73b49ddd-0000-4d10-820b-4239b595bf28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965120312 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1965120312
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3645461166
Short name T154
Test name
Test status
Simulation time 48368100 ps
CPU time 16.8 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 261396 kb
Host smart-d528430c-280d-48c8-bdf2-0dfd7ef192c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645461166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3645461166
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.684016171
Short name T32
Test name
Test status
Simulation time 306312500 ps
CPU time 17.88 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 260204 kb
Host smart-482e2b8b-8197-4855-8398-960a1c7cb3b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684016171 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.684016171
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2858872833
Short name T213
Test name
Test status
Simulation time 13498600 ps
CPU time 15.77 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 260172 kb
Host smart-084aa9b9-b257-4b5d-a0db-353260e4a7d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858872833 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2858872833
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2399776209
Short name T138
Test name
Test status
Simulation time 15097100 ps
CPU time 15.66 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 260100 kb
Host smart-4d03e5f7-b204-4af3-ba03-c5fdd19eac92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399776209 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2399776209
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2156760068
Short name T189
Test name
Test status
Simulation time 706004100 ps
CPU time 464.69 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:34:53 PM PDT 24
Peak memory 263932 kb
Host smart-1c934c73-e9eb-40c5-b03f-5a339a0ff2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156760068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2156760068
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3252967713
Short name T212
Test name
Test status
Simulation time 155323100 ps
CPU time 19.52 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 272092 kb
Host smart-d9e08169-d5f4-4401-a2d5-eb1d349dd2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252967713 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3252967713
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.105961384
Short name T147
Test name
Test status
Simulation time 34344500 ps
CPU time 13.82 seconds
Started Mar 14 12:27:12 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 260148 kb
Host smart-4ed0c0eb-4269-47be-8dd3-84643dd687d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105961384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_csr_rw.105961384
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.656456565
Short name T176
Test name
Test status
Simulation time 60893700 ps
CPU time 32.79 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 261768 kb
Host smart-05218ae2-8574-43fc-a9d5-17802b9f445c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656456565 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.656456565
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3058992571
Short name T168
Test name
Test status
Simulation time 16830100 ps
CPU time 12.92 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:29 PM PDT 24
Peak memory 260120 kb
Host smart-b74999ee-a3f9-48bd-83a6-4dd0aebd5d9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058992571 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3058992571
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3010035260
Short name T140
Test name
Test status
Simulation time 46793700 ps
CPU time 15.82 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 260196 kb
Host smart-d50d708b-d00f-4c5a-8bd0-5d219693201e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010035260 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3010035260
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2809189401
Short name T87
Test name
Test status
Simulation time 106931100 ps
CPU time 18.62 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:24 PM PDT 24
Peak memory 263920 kb
Host smart-0ac6a0bb-0085-4539-a499-f4bd9edfbf7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809189401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2809189401
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2445732938
Short name T174
Test name
Test status
Simulation time 39113100 ps
CPU time 18.47 seconds
Started Mar 14 12:27:23 PM PDT 24
Finished Mar 14 12:27:41 PM PDT 24
Peak memory 271980 kb
Host smart-e037e560-5745-4359-bd9b-0221cbab463b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445732938 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2445732938
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.535240001
Short name T185
Test name
Test status
Simulation time 24304300 ps
CPU time 14.13 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 260268 kb
Host smart-6851ca70-78d5-4054-9219-fd11e34e9af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535240001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.535240001
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1497526415
Short name T98
Test name
Test status
Simulation time 28841200 ps
CPU time 13.26 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 262576 kb
Host smart-9d0d99b2-8e73-4151-acbc-d7143a72587f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497526415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1497526415
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3140596828
Short name T156
Test name
Test status
Simulation time 37776300 ps
CPU time 17.52 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 262292 kb
Host smart-c49a16f9-a722-4453-b3a3-e404f2b251a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140596828 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3140596828
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.419439260
Short name T167
Test name
Test status
Simulation time 41190100 ps
CPU time 13.12 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 260056 kb
Host smart-6e015d27-e61f-4963-9728-270a8551fdce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419439260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.419439260
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.714007126
Short name T135
Test name
Test status
Simulation time 38938200 ps
CPU time 15.51 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 260324 kb
Host smart-2f2da4e9-1822-4e5f-a471-be3b04c0e51c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714007126 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.714007126
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3822517602
Short name T187
Test name
Test status
Simulation time 356719300 ps
CPU time 911.19 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 263980 kb
Host smart-2fc4dbc5-1915-458f-9623-a7fcdb4a2990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822517602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3822517602
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3522688792
Short name T191
Test name
Test status
Simulation time 73883700 ps
CPU time 18.36 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 278456 kb
Host smart-4afa6ff2-7c2a-4ac5-a3ff-931a68459a51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522688792 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3522688792
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2214143603
Short name T69
Test name
Test status
Simulation time 127979600 ps
CPU time 17.04 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 260152 kb
Host smart-8b5a1aa7-c4fe-4676-86fb-740feda7d056
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214143603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.2214143603
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.293535795
Short name T28
Test name
Test status
Simulation time 92329800 ps
CPU time 16.19 seconds
Started Mar 14 12:27:27 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 261900 kb
Host smart-b54981c0-9701-45e3-94c3-ebd18ee023ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293535795 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.293535795
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.842359891
Short name T146
Test name
Test status
Simulation time 18395700 ps
CPU time 13.01 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:24 PM PDT 24
Peak memory 260124 kb
Host smart-e93bd4eb-8240-4166-925b-71b12099667c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842359891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.842359891
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.879363750
Short name T71
Test name
Test status
Simulation time 18574700 ps
CPU time 13.1 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 260168 kb
Host smart-c057a09b-7605-4379-8625-2f17614dedb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879363750 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.879363750
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.963284918
Short name T18
Test name
Test status
Simulation time 37799600 ps
CPU time 15.46 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 272044 kb
Host smart-88fdc893-1a3e-4638-8c69-ad968bcc64b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963284918 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.963284918
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3936338619
Short name T75
Test name
Test status
Simulation time 483956600 ps
CPU time 16.48 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 260104 kb
Host smart-6f475a82-0106-485b-ac81-722365465ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936338619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.3936338619
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3895797376
Short name T114
Test name
Test status
Simulation time 30060000 ps
CPU time 13.57 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 261392 kb
Host smart-d09f8242-482b-407b-948b-8f07dfa1e652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895797376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3895797376
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.603583062
Short name T210
Test name
Test status
Simulation time 313788600 ps
CPU time 29.88 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:37 PM PDT 24
Peak memory 260104 kb
Host smart-c43ceaca-947c-4e9a-b699-5d04522b48c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603583062 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.603583062
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3075101948
Short name T188
Test name
Test status
Simulation time 43236400 ps
CPU time 13.51 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 260128 kb
Host smart-61e99658-579c-4486-af87-40fd9bab301b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075101948 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3075101948
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.223240701
Short name T78
Test name
Test status
Simulation time 19068600 ps
CPU time 12.98 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 260240 kb
Host smart-b3cd3ea9-ac0f-43c3-aace-bd05b6ca7b60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223240701 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.223240701
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3506660376
Short name T177
Test name
Test status
Simulation time 362078800 ps
CPU time 14.76 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 263640 kb
Host smart-9366da2c-9f51-4526-87fa-3ccc7a232ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506660376 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3506660376
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4152567200
Short name T171
Test name
Test status
Simulation time 48732400 ps
CPU time 14.6 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 260356 kb
Host smart-cb13a51d-55d2-47cc-969b-eced62c45b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152567200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.4152567200
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.781644327
Short name T105
Test name
Test status
Simulation time 29834500 ps
CPU time 13.37 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 262616 kb
Host smart-3c0268aa-67c5-4b3d-ba3d-4c99546e9892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781644327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.781644327
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2997524196
Short name T173
Test name
Test status
Simulation time 192711300 ps
CPU time 18.23 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 260264 kb
Host smart-53593162-7c69-487f-bd67-1572bf9bf0e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997524196 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2997524196
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2207877656
Short name T128
Test name
Test status
Simulation time 11302700 ps
CPU time 13.09 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 260052 kb
Host smart-ec92603d-c807-4ad2-92cb-a63530e86896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207877656 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2207877656
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3347967137
Short name T132
Test name
Test status
Simulation time 27590200 ps
CPU time 15.81 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 260248 kb
Host smart-7bbbf959-f619-462f-9455-6e32fe429479
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347967137 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.3347967137
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.687215652
Short name T65
Test name
Test status
Simulation time 1584618100 ps
CPU time 386.12 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:33:29 PM PDT 24
Peak memory 263968 kb
Host smart-b6f84664-9806-4eb1-82e5-eee2c173e1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687215652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.687215652
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2953670913
Short name T211
Test name
Test status
Simulation time 74187100 ps
CPU time 16.14 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 260208 kb
Host smart-0f4e0404-08cc-4d8c-9b6b-798cd74e4e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953670913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2953670913
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1748544708
Short name T103
Test name
Test status
Simulation time 95774800 ps
CPU time 13.3 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 262604 kb
Host smart-e3fe16a9-864c-47eb-9fc0-195bcda08d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748544708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1748544708
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1330401338
Short name T150
Test name
Test status
Simulation time 801835700 ps
CPU time 18.64 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:15 PM PDT 24
Peak memory 262292 kb
Host smart-d9722229-fd7c-4c18-88af-d6a3ff06cdd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330401338 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1330401338
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1683077088
Short name T27
Test name
Test status
Simulation time 32556300 ps
CPU time 15.31 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 260204 kb
Host smart-9cb2bed3-5e52-4619-b55a-57152aad595d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683077088 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.1683077088
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.762868737
Short name T80
Test name
Test status
Simulation time 120100900 ps
CPU time 15.55 seconds
Started Mar 14 12:27:12 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 260240 kb
Host smart-1ea0b764-d5bc-4f7b-943f-deddbcbdd810
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762868737 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.762868737
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1011903988
Short name T175
Test name
Test status
Simulation time 651942500 ps
CPU time 18.8 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 272052 kb
Host smart-28d7453b-823c-4fe5-837a-ad0de911d83e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011903988 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1011903988
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1351010233
Short name T24
Test name
Test status
Simulation time 111505800 ps
CPU time 17 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 260192 kb
Host smart-d05d05a0-571d-4511-adfd-d1ce446fc867
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351010233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1351010233
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3111555462
Short name T108
Test name
Test status
Simulation time 14735000 ps
CPU time 13.37 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 261624 kb
Host smart-fe45c891-4286-43c4-b5de-d63a9bba859c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111555462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3111555462
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2867851394
Short name T162
Test name
Test status
Simulation time 175751700 ps
CPU time 18.46 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:15 PM PDT 24
Peak memory 260272 kb
Host smart-9aa7e1a5-34cf-4a60-8d50-56c863cebd1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867851394 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2867851394
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2348120871
Short name T148
Test name
Test status
Simulation time 13773000 ps
CPU time 15.39 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 260080 kb
Host smart-24cf1190-a769-4e46-a42e-ce668bc8a38e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348120871 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2348120871
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4819181
Short name T127
Test name
Test status
Simulation time 19096400 ps
CPU time 15.14 seconds
Started Mar 14 12:26:57 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 260120 kb
Host smart-9c6d76a2-271e-49f9-811c-3f3eb67e858d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4819181 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.4819181
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3423186674
Short name T215
Test name
Test status
Simulation time 431850300 ps
CPU time 18.91 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 271948 kb
Host smart-f7019192-a1f1-405a-94ab-99a0645d938e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423186674 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3423186674
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.676778849
Short name T10
Test name
Test status
Simulation time 59705700 ps
CPU time 17.33 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 261596 kb
Host smart-7879eb45-c019-4f39-9051-df9dff89fa48
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676778849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_csr_rw.676778849
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3777574623
Short name T40
Test name
Test status
Simulation time 79784800 ps
CPU time 13.29 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 260692 kb
Host smart-0e9200ba-5dc8-423a-aa7c-a0f62721a006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777574623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
3777574623
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3409796430
Short name T41
Test name
Test status
Simulation time 34762100 ps
CPU time 14.69 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 260124 kb
Host smart-5c6828d8-08b9-4e17-9891-b59d906361e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409796430 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3409796430
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3882184502
Short name T201
Test name
Test status
Simulation time 19284600 ps
CPU time 15.5 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 260164 kb
Host smart-5581c95b-8a8e-4e5e-a75b-e79b611d96ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882184502 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3882184502
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2093575563
Short name T131
Test name
Test status
Simulation time 11594800 ps
CPU time 15.29 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:34 PM PDT 24
Peak memory 260088 kb
Host smart-f9225594-a21e-4fc5-99a2-c3cbcba3d6f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093575563 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2093575563
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3409984973
Short name T56
Test name
Test status
Simulation time 123010100 ps
CPU time 15.5 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 263960 kb
Host smart-032271c8-5db6-4b74-a255-dc80949ac77e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409984973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3409984973
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1554628923
Short name T166
Test name
Test status
Simulation time 2279107600 ps
CPU time 468.14 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:34:58 PM PDT 24
Peak memory 263860 kb
Host smart-38c6c722-6d74-4668-b821-fa604e0e24e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554628923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1554628923
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2321428160
Short name T163
Test name
Test status
Simulation time 1712448100 ps
CPU time 50.6 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 260144 kb
Host smart-0a811090-15c6-442b-90d1-857eda132bfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321428160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2321428160
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3288604326
Short name T139
Test name
Test status
Simulation time 663916700 ps
CPU time 61.58 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:54 PM PDT 24
Peak memory 260116 kb
Host smart-ffe3d968-4b6b-40b9-97eb-7d6a624cc359
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288604326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.3288604326
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3433878906
Short name T38
Test name
Test status
Simulation time 54448100 ps
CPU time 31.26 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 260196 kb
Host smart-b6526f30-3043-481a-aa1a-f21220cace29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433878906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3433878906
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1889874938
Short name T194
Test name
Test status
Simulation time 48766200 ps
CPU time 17.62 seconds
Started Mar 14 12:26:59 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 271452 kb
Host smart-5117d3df-c44b-4614-8515-3a099193d0e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889874938 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1889874938
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2675767268
Short name T155
Test name
Test status
Simulation time 635125300 ps
CPU time 16.92 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 260192 kb
Host smart-ccf0d4f5-4cf4-422d-ad3f-4670f7db4561
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675767268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.2675767268
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.589558729
Short name T113
Test name
Test status
Simulation time 17032100 ps
CPU time 13.73 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:26:54 PM PDT 24
Peak memory 262472 kb
Host smart-aec266b4-5b13-4417-8734-84bc52c320be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589558729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.589558729
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1233349755
Short name T3
Test name
Test status
Simulation time 66701200 ps
CPU time 13.52 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 262408 kb
Host smart-e0233b78-e2b5-4ac3-9065-625c4afefd95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233349755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1233349755
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1757755071
Short name T172
Test name
Test status
Simulation time 36789500 ps
CPU time 17.3 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 260076 kb
Host smart-f40a02e9-d3bc-490b-a028-e43d28fc03b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757755071 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1757755071
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3124150670
Short name T141
Test name
Test status
Simulation time 102021700 ps
CPU time 15.41 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 260148 kb
Host smart-8af5d84a-ac1d-4e93-9321-82194767ddcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124150670 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3124150670
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1662230504
Short name T74
Test name
Test status
Simulation time 44389700 ps
CPU time 15.34 seconds
Started Mar 14 12:26:39 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 260044 kb
Host smart-e22e307e-647a-4bc7-b12b-1d02f896ff41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662230504 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1662230504
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4179812069
Short name T85
Test name
Test status
Simulation time 131940800 ps
CPU time 15.75 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 263920 kb
Host smart-333227d2-9aba-4074-93ab-ddb330682bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179812069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.4
179812069
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.769834939
Short name T4
Test name
Test status
Simulation time 2338345500 ps
CPU time 456.33 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:34:24 PM PDT 24
Peak memory 263888 kb
Host smart-539c27df-4d83-4c74-a336-53f1e7d36ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769834939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.769834939
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.779884940
Short name T117
Test name
Test status
Simulation time 55902100 ps
CPU time 13.34 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 262200 kb
Host smart-e547f717-ba61-4b11-a96b-3e1f622ab02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779884940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.779884940
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3786312151
Short name T112
Test name
Test status
Simulation time 26738500 ps
CPU time 13.37 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 262620 kb
Host smart-b14d1e96-4a49-475e-89be-49c9d0c5d6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786312151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
3786312151
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.846983740
Short name T209
Test name
Test status
Simulation time 48597200 ps
CPU time 13.38 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 262560 kb
Host smart-8a399379-ec27-495e-b8ce-27ba227a4ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846983740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.846983740
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3975142794
Short name T121
Test name
Test status
Simulation time 17080600 ps
CPU time 13.71 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 261580 kb
Host smart-485a0f6e-c2cd-420b-a948-0a97f73a78a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975142794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
3975142794
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3861238298
Short name T83
Test name
Test status
Simulation time 26850000 ps
CPU time 13.29 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 262592 kb
Host smart-f8744bb4-39f6-4551-976c-20d63907da98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861238298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3861238298
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1516457541
Short name T2
Test name
Test status
Simulation time 14465800 ps
CPU time 13.45 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 262356 kb
Host smart-a696fc87-fcc4-43e9-b213-20ce6c40b2db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516457541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1516457541
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2905742416
Short name T181
Test name
Test status
Simulation time 448387300 ps
CPU time 50.66 seconds
Started Mar 14 12:26:45 PM PDT 24
Finished Mar 14 12:27:36 PM PDT 24
Peak memory 260124 kb
Host smart-295a590c-e689-4024-b3ea-babbfb2e6977
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905742416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2905742416
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1415585490
Short name T152
Test name
Test status
Simulation time 9087079700 ps
CPU time 85.58 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 262208 kb
Host smart-320fb8e4-014c-45d8-a188-0183aff32d73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415585490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1415585490
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4264431530
Short name T199
Test name
Test status
Simulation time 108429700 ps
CPU time 30.93 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 260236 kb
Host smart-8a4cb954-3f18-47d6-8c6f-b582420a88eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264431530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.4264431530
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.290312107
Short name T202
Test name
Test status
Simulation time 84664300 ps
CPU time 18.2 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 272100 kb
Host smart-2d315905-a68d-4b7b-8ba1-84dda4b41c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290312107 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.290312107
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3248483148
Short name T116
Test name
Test status
Simulation time 17000400 ps
CPU time 13.2 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 262416 kb
Host smart-14ff1da5-4669-4614-9817-02b406a151dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248483148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
248483148
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3825626560
Short name T47
Test name
Test status
Simulation time 33665600 ps
CPU time 13.35 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 261836 kb
Host smart-4a48c1c2-48c3-47f0-8b7f-f822aae2a86e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825626560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3825626560
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.960001671
Short name T82
Test name
Test status
Simulation time 1527916400 ps
CPU time 21.25 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:24 PM PDT 24
Peak memory 260104 kb
Host smart-7bc9d468-7e02-4c84-bac5-01c1b2f2c0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960001671 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.960001671
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3924918211
Short name T136
Test name
Test status
Simulation time 73604800 ps
CPU time 15.52 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 260216 kb
Host smart-0b441aa0-ea01-4b5d-b49f-ec989870551d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924918211 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3924918211
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1145353624
Short name T169
Test name
Test status
Simulation time 25355600 ps
CPU time 15.93 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 260156 kb
Host smart-b6f2a67e-1398-4cdd-bb97-5fac47e9df36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145353624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.1145353624
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1283221657
Short name T67
Test name
Test status
Simulation time 105402100 ps
CPU time 18.58 seconds
Started Mar 14 12:26:48 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 263872 kb
Host smart-f5f35db8-1e0f-4a07-9d81-6173dd37fa8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283221657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
283221657
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.57569396
Short name T70
Test name
Test status
Simulation time 949044400 ps
CPU time 461.34 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:34:32 PM PDT 24
Peak memory 263924 kb
Host smart-926e1506-47f6-4821-a0c9-9718f59bcf80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57569396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_t
l_intg_err.57569396
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.885397512
Short name T125
Test name
Test status
Simulation time 18320100 ps
CPU time 13.32 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 262508 kb
Host smart-6516463f-a530-43c3-bb99-185d0a64eaa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885397512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.885397512
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3361633350
Short name T165
Test name
Test status
Simulation time 54066900 ps
CPU time 13.29 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 262628 kb
Host smart-db00eede-8eae-4a5f-9e3a-5f5b6c232517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361633350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3361633350
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3472097620
Short name T106
Test name
Test status
Simulation time 28812000 ps
CPU time 13.19 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 262600 kb
Host smart-1dc04fc5-bf01-45d5-8d88-805ddb8101a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472097620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3472097620
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.579602938
Short name T104
Test name
Test status
Simulation time 57305500 ps
CPU time 13.53 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:29 PM PDT 24
Peak memory 262612 kb
Host smart-0cbd83e9-d608-4e54-af40-ecd7b871c5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579602938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.579602938
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.212275340
Short name T81
Test name
Test status
Simulation time 1624824900 ps
CPU time 62.47 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:27:42 PM PDT 24
Peak memory 260112 kb
Host smart-f1712d65-6746-40a1-81ed-42e382717e0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212275340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.212275340
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3068639716
Short name T54
Test name
Test status
Simulation time 2135451500 ps
CPU time 39.21 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 260112 kb
Host smart-898ff1b2-1e19-44a9-aecf-c2f587d87837
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068639716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3068639716
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2878161715
Short name T159
Test name
Test status
Simulation time 46778800 ps
CPU time 45.88 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:27:33 PM PDT 24
Peak memory 260088 kb
Host smart-8035ea2e-ea45-4049-a1cc-b8ffbcbbb498
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878161715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.2878161715
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4178547806
Short name T19
Test name
Test status
Simulation time 86737900 ps
CPU time 16.92 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 270376 kb
Host smart-e0b16b63-d32a-4b23-9140-ee26a7afe0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178547806 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.4178547806
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.733944091
Short name T37
Test name
Test status
Simulation time 39846300 ps
CPU time 13.81 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 260084 kb
Host smart-3ba39e68-185c-4bc5-bb9d-089cb84a2fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733944091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.733944091
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2018192259
Short name T115
Test name
Test status
Simulation time 48339400 ps
CPU time 13.14 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 261380 kb
Host smart-4c473728-bc85-48d8-a621-b34dd4d54191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018192259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
018192259
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1231210149
Short name T101
Test name
Test status
Simulation time 45751900 ps
CPU time 13.16 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 262424 kb
Host smart-8b62be8d-c205-44d2-98b4-f222981043fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231210149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.1231210149
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3568756560
Short name T153
Test name
Test status
Simulation time 646249200 ps
CPU time 30.39 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 260156 kb
Host smart-531d5fbe-2f83-4cad-8cd6-42a84c9390c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568756560 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3568756560
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1152167399
Short name T160
Test name
Test status
Simulation time 41279200 ps
CPU time 12.86 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 260112 kb
Host smart-3391323b-4b65-4280-bb0f-1932c84e6754
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152167399 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.1152167399
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3009261662
Short name T184
Test name
Test status
Simulation time 37046000 ps
CPU time 15.75 seconds
Started Mar 14 12:26:35 PM PDT 24
Finished Mar 14 12:26:52 PM PDT 24
Peak memory 260196 kb
Host smart-cafd88c9-3053-47c6-8c2e-90b37391b67b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009261662 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3009261662
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2643504207
Short name T63
Test name
Test status
Simulation time 176820000 ps
CPU time 15.74 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 263864 kb
Host smart-16e43df1-73e1-4d9a-9836-f48f2be5aa90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643504207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
643504207
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2148313078
Short name T178
Test name
Test status
Simulation time 673186700 ps
CPU time 455.01 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:34:26 PM PDT 24
Peak memory 262680 kb
Host smart-e29559b1-f4c0-4649-80be-9d55342dd75d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148313078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2148313078
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1250992330
Short name T107
Test name
Test status
Simulation time 15072700 ps
CPU time 13.4 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 262340 kb
Host smart-730494ae-66a4-43d0-b76e-8eacf2d9566d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250992330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1250992330
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2929048599
Short name T94
Test name
Test status
Simulation time 56478200 ps
CPU time 13.36 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 260604 kb
Host smart-b2327e3a-d1c0-4950-9e9e-1fb00d7cedd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929048599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2929048599
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.169850004
Short name T124
Test name
Test status
Simulation time 16749500 ps
CPU time 13.58 seconds
Started Mar 14 12:27:37 PM PDT 24
Finished Mar 14 12:27:51 PM PDT 24
Peak memory 262288 kb
Host smart-3f4ae236-2c4d-4993-9ec8-5c50aa2f9332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169850004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.169850004
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3869721276
Short name T95
Test name
Test status
Simulation time 57903900 ps
CPU time 13.3 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 262308 kb
Host smart-d9d95325-55c5-474c-8364-f282f96f402e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869721276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3869721276
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2156822751
Short name T214
Test name
Test status
Simulation time 16942500 ps
CPU time 13.23 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 262528 kb
Host smart-cbb89cbd-d13d-42cc-9f01-48f413a79200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156822751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2156822751
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2262218061
Short name T97
Test name
Test status
Simulation time 47060600 ps
CPU time 13.18 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 262336 kb
Host smart-218f6706-dfce-4ff4-8c8c-de0e343577e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262218061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2262218061
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2455387562
Short name T123
Test name
Test status
Simulation time 46086000 ps
CPU time 13.47 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 262380 kb
Host smart-73019262-050a-4c68-b5ee-bfb0ec762de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455387562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2455387562
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1947142872
Short name T161
Test name
Test status
Simulation time 403928900 ps
CPU time 16.41 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 272020 kb
Host smart-4926bdd3-eefc-41aa-afd6-fa601e62ce65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947142872 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1947142872
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3334649809
Short name T179
Test name
Test status
Simulation time 146200500 ps
CPU time 16.53 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 260120 kb
Host smart-29f03fdd-1833-4bfb-b7bd-1a3a24dccf95
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334649809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3334649809
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.432053898
Short name T111
Test name
Test status
Simulation time 55637300 ps
CPU time 13.11 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 262268 kb
Host smart-cd34ce34-273e-4ebe-8ff8-e2c40faea563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432053898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.432053898
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2820661115
Short name T33
Test name
Test status
Simulation time 211404400 ps
CPU time 18.46 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 260244 kb
Host smart-2d3c93c4-5433-473b-9ade-7eed24ef1c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820661115 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.2820661115
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4157131459
Short name T149
Test name
Test status
Simulation time 24377300 ps
CPU time 15.77 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 260172 kb
Host smart-7d5b6f94-d58b-432a-8ebc-1f70e9dd2cb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157131459 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.4157131459
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.444920652
Short name T129
Test name
Test status
Simulation time 13984900 ps
CPU time 15.58 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 260200 kb
Host smart-2bcd4e0b-87a6-4069-b3e0-94d8948b4990
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444920652 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.444920652
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.336408365
Short name T22
Test name
Test status
Simulation time 52351500 ps
CPU time 18.82 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 263928 kb
Host smart-e56554a0-e81c-4249-b921-5db3eea3e3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336408365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.336408365
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1347085543
Short name T186
Test name
Test status
Simulation time 81669400 ps
CPU time 18.03 seconds
Started Mar 14 12:26:27 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 272104 kb
Host smart-e81a5370-516b-4ab7-bb4d-34cd60a527e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347085543 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1347085543
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1132024966
Short name T200
Test name
Test status
Simulation time 191642800 ps
CPU time 16.84 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 260228 kb
Host smart-60ca66f0-5391-49ac-af3b-3bc861873cc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132024966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1132024966
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3327472085
Short name T1
Test name
Test status
Simulation time 24553900 ps
CPU time 13.32 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 262248 kb
Host smart-2cba33c1-79ed-4d59-8eb0-06fd5dd437eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327472085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
327472085
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2502255118
Short name T50
Test name
Test status
Simulation time 2561653200 ps
CPU time 34.44 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 263864 kb
Host smart-e202e0a4-5d74-459f-b5c4-d3aaa1083f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502255118 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2502255118
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.872806514
Short name T143
Test name
Test status
Simulation time 13538900 ps
CPU time 13.19 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 260128 kb
Host smart-da55fe2c-2020-47dc-a43d-0fae24dab66e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872806514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.872806514
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1112957004
Short name T39
Test name
Test status
Simulation time 14013200 ps
CPU time 15.6 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 260072 kb
Host smart-f4e867e6-e7a6-4266-bc38-fb715b31ef75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112957004 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1112957004
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.146163647
Short name T205
Test name
Test status
Simulation time 81612400 ps
CPU time 17.02 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 263984 kb
Host smart-bc51d897-df4d-47ab-bd92-9ff79cc98016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146163647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.146163647
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1258593845
Short name T89
Test name
Test status
Simulation time 457318000 ps
CPU time 460.63 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:34:25 PM PDT 24
Peak memory 263756 kb
Host smart-3c88ccc8-035c-4432-9895-04a820ea9cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258593845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.1258593845
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.75773331
Short name T20
Test name
Test status
Simulation time 90600500 ps
CPU time 14.84 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 271768 kb
Host smart-4c4cc7f1-a3c0-49b9-b024-7749b3a67681
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75773331 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.75773331
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2721097870
Short name T157
Test name
Test status
Simulation time 90289100 ps
CPU time 16.51 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 260124 kb
Host smart-7ee6a570-145b-4da6-a6e6-6934b63cb659
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721097870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2721097870
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.129281402
Short name T207
Test name
Test status
Simulation time 41003800 ps
CPU time 13.24 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 262436 kb
Host smart-15db6a8a-b7c6-4e2b-8b83-bb9bafeb66f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129281402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.129281402
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1850833295
Short name T51
Test name
Test status
Simulation time 184185900 ps
CPU time 19.75 seconds
Started Mar 14 12:27:01 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 260168 kb
Host smart-f5ff3e4d-c786-4c98-8b85-eadbbc564254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850833295 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1850833295
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2708388515
Short name T13
Test name
Test status
Simulation time 69522900 ps
CPU time 15.46 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 260092 kb
Host smart-47e41dea-3bd8-444d-b8db-a9743062bcf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708388515 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2708388515
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.223658311
Short name T192
Test name
Test status
Simulation time 44942400 ps
CPU time 13.02 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 260256 kb
Host smart-1a8f4d6a-e822-4048-a5be-019007f3bc37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223658311 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.223658311
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.105492196
Short name T119
Test name
Test status
Simulation time 87210700 ps
CPU time 17.8 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 263892 kb
Host smart-0a8d6227-c30e-4411-bea9-3c5e2bfb039f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105492196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.105492196
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2357145258
Short name T17
Test name
Test status
Simulation time 173167000 ps
CPU time 17.1 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 271088 kb
Host smart-dfa0c6ad-4236-42aa-9c36-6ca67d065ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357145258 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2357145258
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2037585302
Short name T183
Test name
Test status
Simulation time 163793900 ps
CPU time 16.79 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 263840 kb
Host smart-4aeac61c-a036-4eea-9cb9-6fcd2430d870
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037585302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2037585302
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.353770463
Short name T29
Test name
Test status
Simulation time 124342300 ps
CPU time 18.98 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 262324 kb
Host smart-8d76d998-3593-461f-8a3a-1f7afdf6ae59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353770463 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.353770463
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1473631368
Short name T137
Test name
Test status
Simulation time 36812500 ps
CPU time 15.56 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 260276 kb
Host smart-280f1c09-3c51-4cca-9aa3-1b9d49fdd2e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473631368 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1473631368
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1232383417
Short name T25
Test name
Test status
Simulation time 14181900 ps
CPU time 15.33 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 260124 kb
Host smart-97496348-454a-430f-b1ab-742e0ee24694
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232383417 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1232383417
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.364003046
Short name T195
Test name
Test status
Simulation time 98578700 ps
CPU time 19.37 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 263972 kb
Host smart-29e4aaca-fd66-44bc-ace0-77c0653e88a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364003046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.364003046
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2083342047
Short name T164
Test name
Test status
Simulation time 753374500 ps
CPU time 459.3 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 260404 kb
Host smart-05e264c3-1958-48e5-902f-481261e46167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083342047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2083342047
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4122796529
Short name T180
Test name
Test status
Simulation time 320860600 ps
CPU time 18.47 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 270224 kb
Host smart-cce4f9c5-8798-4259-aafe-7a47e2f3b0de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122796529 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.4122796529
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.136784807
Short name T206
Test name
Test status
Simulation time 45740900 ps
CPU time 17.34 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 260048 kb
Host smart-cb93376a-e894-4d8f-bece-f4278cbc01db
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136784807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.136784807
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1896493670
Short name T118
Test name
Test status
Simulation time 17126600 ps
CPU time 13.34 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 262148 kb
Host smart-c5d75ef1-c683-49b3-bfe4-cc7f89262fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896493670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
896493670
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.498129113
Short name T35
Test name
Test status
Simulation time 64565100 ps
CPU time 33.63 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 260216 kb
Host smart-799924e9-02be-46bd-928c-d8b8f6c9d41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498129113 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.498129113
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2650756060
Short name T196
Test name
Test status
Simulation time 33170900 ps
CPU time 13.14 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 260116 kb
Host smart-1a83aa5a-655b-4140-bd65-6559ed385163
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650756060 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2650756060
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1454877076
Short name T144
Test name
Test status
Simulation time 13513400 ps
CPU time 15.22 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 260068 kb
Host smart-13432424-0361-4502-83a5-5baefbe6c5c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454877076 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1454877076
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3236425968
Short name T64
Test name
Test status
Simulation time 52014200 ps
CPU time 19.38 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 263896 kb
Host smart-099f1650-d82d-4324-808f-a8055ed33aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236425968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3
236425968
Directory /workspace/9.flash_ctrl_tl_errors/latest
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