Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
42.69 38.50 39.75 52.26 0.00 26.39 99.24


Total modules in report: 79
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
flash_ctrl_region_cfg 0.00 0.00
  prim_fifo_sync_cnt 0.00 0.00 0.00 0.00
  prim_lc_sync 0.00 0.00
flash_ctrl_arb 0.00 0.00 0.00 0.00 0.00
  flash_mp_data_region_sel 0.00 0.00 0.00 0.00
prim_sparse_fsm_flop 0.00 0.00
  prim_count 0.00 0.00
prim_generic_ram_1p 0.00 0.00 0.00
prim_secded_hamming_76_68_enc 0.00 0.00
prim_arbiter_tree 0.00 0.00 0.00 0.00
prim_generic_and2 0.00 0.00
prim_mubi4_sender 0.00 0.00 0.00
  flash_ctrl_info_cfg 0.00 0.00
flash_phy_prog 0.00 0.00 0.00 0.00 0.00
  prim_onehot_check 0.00 0.00
flash_mp 0.00 0.00 0.00 0.00
prim_gf_mult 0.00 0.00 0.00 0.00
flash_phy_erase 0.00 0.00 0.00 0.00 0.00
  prim_intr_hw 0.00 0.00 0.00 0.00
flash_phy_rd 0.00 0.00 0.00 0.00
flash_ctrl_lcmgr 0.00 0.00 0.00 0.00 0.00
flash_ctrl_rd 0.00 0.00 0.00 0.00 0.00
tlul_lc_gate 0.00 0.00 0.00 0.00 0.00
prim_arbiter_tree_dup 0.00 0.00 0.00 0.00
flash_phy_scramble 0.00 0.00 0.00 0.00
  tlul_adapter_sram 0.00 0.00 0.00 0.00
flash_phy_rd_buf_dep 0.00 0.00 0.00 0.00
prim_sync_reqack 0.00 0.00 0.00 0.00
prim_secded_hamming_76_68_dec 0.00 0.00 0.00
flash_ctrl_erase 0.00 0.00 0.00 0.00
prim_generic_flash_bank 0.00 0.00 0.00 0.00 0.00
tlul_sram_byte 0.00 0.00
flash_ctrl_phy_cov_if 0.00 0.00 0.00 0.00
prim_lfsr 0.00 0.00
flash_phy_core 0.00 0.00 0.00 0.00 0.00
flash_phy 0.00 0.00 0.00 0.00
prim_generic_flash 0.00 0.00
prim_prince 0.00 0.00
prim_generic_flop 0.00 0.00 0.00
prim_arbiter_fixed 0.00 0.00 0.00 0.00
flash_phy_rd_buffers 0.00 0.00 0.00 0.00
flash_ctrl_prog 0.00 0.00 0.00 0.00
  prim_mubi4_sync 0.00 0.00
prim_secded_hamming_72_64_enc 0.00 0.00
flash_ctrl 16.65 0.00 0.00 66.62 0.00
  prim_fifo_sync 28.57 14.29 0.00 0.00 100.00
tlul_assert 32.98 0.00 0.00 98.95
tlul_err_resp 57.80 76.92 40.91 55.56
prim_subreg_shadow 93.27 100.00 73.08 100.00 100.00
  tlul_rsp_intg_gen 93.33 86.67 100.00
tlul_socket_1n 97.25 100.00 93.33 95.65 100.00
tlul_adapter_reg 97.96 100.00 91.84 100.00 100.00
  prim_subreg_arb 98.25 100.00 94.76 100.00
flash_ctrl_core_reg_top 99.78 100.00 99.10 100.00 100.00
flash_ctrl_prim_reg_top 99.83 100.00 99.30 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_subreg_ext 100.00 100.00
flash_ctrl_core_csr_assert_fpv 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_flash
tlul_data_integ_enc
prim_reg_we_check
prim_blanker
prim_buf
prim_flop
prim_flop_2sync
tb
prim_and2
prim_sec_anchor_buf
prim_ram_1p