---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	2308514	5014	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	2308514	1134	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	2308514	2699	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	2308514	1688	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	2308514	2560	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	2308514	2009	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	2308514	2562	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	2308514	2766	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	2308514	2093	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	2308514	1959	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	2308514	2498	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	2308514	2440	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	2308514	1473	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	2308514	1467	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	2308514	1786	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	2308514	1291	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	2308514	1657	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	2308514	1729	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	2308514	753	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	2308514	1289	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	2308514	1191	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	2308514	1535	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	2308514	2596	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	2308514	1272	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	2308514	1888	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	2308514	2112	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	2308514	1723	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	2308514	1626	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	2308514	2402	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	2308514	2113	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	2308514	2114	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	2308514	2366	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	2308514	2458	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	2308514	1816	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	2308514	2465	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	2308514	2594	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	2308514	2640	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	2308514	1626	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	2308514	1644	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	2308514	1720	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	2308514	1232	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	2308514	1740	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	2308514	1295	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	2308514	1287	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	2308514	1707	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	2308514	1202	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	2308514	950	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	2308514	1340	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	2308514	2453	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	2308514	1002	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	2308514	2466	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	2308514	1609	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	2308514	937	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	2308514	1740	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	2308514	1742	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	2308514	1870	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	2308514	1972	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	2308514	1894	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	2308514	1859	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	2308514	1843	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	2308514	1548	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	2308514	1952	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	2308514	1378	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	2308514	1776	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	2308514	1689	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	2308514	1897	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	2308514	1485	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	2308514	1352	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	2308514	1428	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	2308514	2292	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	2308514	2179	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	2308514	1792	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	2308514	2710	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	2308514	2792	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	2308514	2615	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	2308514	2361	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	2308514	2552	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	2308514	1419	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	2308514	1776	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	2308514	1678	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	2308514	1164	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	2308514	1782	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	2308514	1748	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	2308514	467	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	2308514	1548	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	2308514	1273	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	2308514	1675	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2308514	644490	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2308514	2228562	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2308514	661396	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2308514	2228562	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
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tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	215	215	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2308631	192041	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2308514	7130	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2308631	321972	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2308631	302141	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2308514	5417	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2308631	644490	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2308631	661396	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2308631	644490	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2308631	661396	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2308631	661396	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2308631	661396	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2308514	5204	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2308514	5424	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	2308514	60937	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	2308514	60937	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	2308514	43119	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	2308514	17818	0	0
tb.dut.u_reg_core.en2addrHit	0	0	2308514	382283	0	0
tb.dut.u_reg_core.reAfterRv	0	0	2308514	382283	0	0
tb.dut.u_reg_core.rePulse	0	0	2308514	277274	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	215	215	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	2308514	644490	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	2308514	661396	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	2308514	8818	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	2308514	7731	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	2308514	4358	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	2308514	3764	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	2308514	619234	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	2308514	649901	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	2308514	2228562	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	215	215	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	215	215	0	0
tb.dut.u_reg_core.wePulse	0	0	2308514	105009	0	0

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2308631	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2308631	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2308631	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2308631	6332	6332	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2308631	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2308631	2	2	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2308631	4	4	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2308631	13984	13984	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2308631	64711	64711	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2308631	49686	49686	195

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2308631	6332	6332	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2308631	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2308631	2	2	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2308631	4	4	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2308631	13984	13984	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2308631	64711	64711	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2308631	49686	49686	195