Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
20 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T12 |
1 |
| others[1] |
10 |
1 |
|
T14 |
1 |
|
T42 |
1 |
|
T116 |
1 |
| others[2] |
17 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T92 |
1 |
| others[3] |
27 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T9 |
1 |
| false |
6 |
1 |
|
T84 |
1 |
|
T45 |
1 |
|
T117 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T2 |
1 |
|
T118 |
1 |
|
T45 |
1 |
| others[1] |
10 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T100 |
1 |
| others[2] |
15 |
1 |
|
T7 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| others[3] |
36 |
1 |
|
T11 |
1 |
|
T9 |
1 |
|
T8 |
1 |
| false |
9 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T101 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T79 |
1 |
| others[1] |
20 |
1 |
|
T12 |
1 |
|
T14 |
1 |
|
T26 |
1 |
| others[2] |
17 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| others[3] |
25 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| false |
5 |
1 |
|
T63 |
1 |
|
T59 |
1 |
|
T108 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
19 |
1 |
|
T15 |
1 |
|
T92 |
1 |
|
T76 |
1 |
| others[1] |
17 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T12 |
1 |
| others[2] |
18 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
| others[3] |
18 |
1 |
|
T8 |
1 |
|
T84 |
1 |
|
T73 |
1 |
| false |
8 |
1 |
|
T72 |
1 |
|
T107 |
1 |
|
T86 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
20 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T8 |
1 |
| others[1] |
12 |
1 |
|
T43 |
1 |
|
T106 |
1 |
|
T100 |
1 |
| others[2] |
18 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T26 |
1 |
| others[3] |
21 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T7 |
1 |
| false |
9 |
1 |
|
T98 |
1 |
|
T118 |
1 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T26 |
1 |
| others[1] |
17 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T14 |
1 |
| others[2] |
15 |
1 |
|
T72 |
1 |
|
T100 |
1 |
|
T59 |
1 |
| others[3] |
16 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T76 |
1 |
| false |
16 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
18 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T84 |
1 |
| others[1] |
21 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T7 |
1 |
| others[2] |
13 |
1 |
|
T92 |
1 |
|
T21 |
1 |
|
T22 |
1 |
| others[3] |
23 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T8 |
1 |
| false |
5 |
1 |
|
T14 |
1 |
|
T26 |
1 |
|
T98 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
14 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T14 |
1 |
| others[1] |
16 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T26 |
1 |
| others[2] |
22 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| others[3] |
21 |
1 |
|
T9 |
1 |
|
T84 |
1 |
|
T76 |
1 |
| false |
7 |
1 |
|
T11 |
1 |
|
T40 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T15 |
1 |
| others[1] |
17 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T14 |
1 |
| others[2] |
15 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T72 |
1 |
| others[3] |
31 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T26 |
1 |
| false |
5 |
1 |
|
T83 |
1 |
|
T76 |
1 |
|
T85 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T72 |
1 |
| others[1] |
13 |
1 |
|
T8 |
1 |
|
T92 |
1 |
|
T21 |
1 |
| others[2] |
17 |
1 |
|
T2 |
1 |
|
T9 |
1 |
|
T15 |
1 |
| others[3] |
32 |
1 |
|
T1 |
1 |
|
T11 |
1 |
|
T7 |
1 |
| false |
6 |
1 |
|
T12 |
1 |
|
T42 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T8 |
1 |
|
T79 |
1 |
|
T42 |
1 |
| others[1] |
13 |
1 |
|
T3 |
1 |
|
T12 |
1 |
|
T26 |
1 |
| others[2] |
17 |
1 |
|
T1 |
1 |
|
T11 |
1 |
|
T84 |
1 |
| others[3] |
28 |
1 |
|
T7 |
1 |
|
T9 |
1 |
|
T14 |
1 |
| false |
13 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T92 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
14 |
1 |
|
T11 |
1 |
|
T98 |
1 |
|
T102 |
1 |
| others[1] |
22 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T8 |
1 |
| others[2] |
12 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T84 |
1 |
| others[3] |
28 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T79 |
1 |
| false |
4 |
1 |
|
T14 |
1 |
|
T83 |
1 |
|
T72 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T83 |
1 |
| others[1] |
6 |
1 |
|
T72 |
1 |
|
T73 |
1 |
|
T42 |
1 |
| others[2] |
4 |
1 |
|
T1 |
1 |
|
T101 |
1 |
|
T58 |
1 |
| others[3] |
14 |
1 |
|
T26 |
1 |
|
T84 |
1 |
|
T76 |
1 |
| false |
2 |
1 |
|
T44 |
1 |
|
T113 |
1 |
|
- |
- |
| true |
43 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T14 |
1 |
| others[1] |
5 |
1 |
|
T85 |
1 |
|
T113 |
1 |
|
T86 |
1 |
| others[2] |
9 |
1 |
|
T1 |
1 |
|
T79 |
1 |
|
T93 |
1 |
| others[3] |
13 |
1 |
|
T3 |
1 |
|
T76 |
1 |
|
T96 |
1 |
| false |
4 |
1 |
|
T9 |
1 |
|
T115 |
1 |
|
T119 |
1 |
| true |
39 |
1 |
|
T11 |
1 |
|
T7 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T43 |
1 |
|
T44 |
1 |
|
T60 |
1 |
| others[1] |
11 |
1 |
|
T2 |
1 |
|
T83 |
1 |
|
T93 |
1 |
| others[2] |
6 |
1 |
|
T22 |
1 |
|
T56 |
1 |
|
T97 |
1 |
| others[3] |
19 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T8 |
1 |
| false |
4 |
1 |
|
T11 |
1 |
|
T14 |
1 |
|
T102 |
1 |
| true |
35 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
| others[1] |
4 |
1 |
|
T114 |
1 |
|
T60 |
1 |
|
T120 |
1 |
| others[2] |
6 |
1 |
|
T85 |
1 |
|
T59 |
1 |
|
T45 |
1 |
| others[3] |
20 |
1 |
|
T11 |
1 |
|
T21 |
1 |
|
T22 |
1 |
| false |
1 |
1 |
|
T84 |
1 |
|
- |
- |
|
- |
- |
| true |
42 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T14 |
1 |
|
T83 |
1 |
|
T72 |
1 |
| others[1] |
7 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T22 |
1 |
| others[2] |
10 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T84 |
1 |
| others[3] |
15 |
1 |
|
T94 |
1 |
|
T43 |
1 |
|
T85 |
1 |
| false |
6 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T112 |
1 |
| true |
37 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T55 |
1 |
| others[1] |
4 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T76 |
1 |
| others[2] |
8 |
1 |
|
T1 |
1 |
|
T79 |
1 |
|
T43 |
1 |
| others[3] |
11 |
1 |
|
T12 |
1 |
|
T15 |
1 |
|
T83 |
1 |
| false |
8 |
1 |
|
T102 |
1 |
|
T40 |
1 |
|
T63 |
1 |
| true |
43 |
1 |
|
T3 |
1 |
|
T9 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T14 |
1 |
|
T108 |
1 |
|
T46 |
1 |
| others[1] |
9 |
1 |
|
T3 |
1 |
|
T9 |
1 |
|
T72 |
1 |
| others[2] |
6 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T98 |
1 |
| others[3] |
13 |
1 |
|
T7 |
1 |
|
T26 |
1 |
|
T92 |
1 |
| false |
3 |
1 |
|
T43 |
1 |
|
T101 |
1 |
|
T121 |
1 |
| true |
42 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T98 |
1 |
| others[1] |
8 |
1 |
|
T3 |
1 |
|
T12 |
1 |
|
T83 |
1 |
| others[2] |
11 |
1 |
|
T92 |
1 |
|
T94 |
1 |
|
T21 |
1 |
| others[3] |
12 |
1 |
|
T9 |
1 |
|
T73 |
1 |
|
T102 |
1 |
| false |
7 |
1 |
|
T11 |
1 |
|
T14 |
1 |
|
T85 |
1 |
| true |
34 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T83 |
1 |
|
T76 |
1 |
|
T98 |
1 |
| others[1] |
4 |
1 |
|
T42 |
1 |
|
T100 |
1 |
|
T105 |
1 |
| others[2] |
12 |
1 |
|
T2 |
1 |
|
T72 |
1 |
|
T44 |
1 |
| others[3] |
13 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T12 |
1 |
| false |
4 |
1 |
|
T3 |
1 |
|
T102 |
1 |
|
T45 |
1 |
| true |
40 |
1 |
|
T11 |
1 |
|
T9 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T92 |
1 |
|
T98 |
1 |
|
T40 |
1 |
| others[1] |
6 |
1 |
|
T96 |
1 |
|
T42 |
1 |
|
T108 |
1 |
| others[2] |
9 |
1 |
|
T79 |
1 |
|
T102 |
1 |
|
T118 |
1 |
| others[3] |
13 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T72 |
1 |
| false |
7 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| true |
39 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T11 |
1 |
|
T26 |
1 |
|
T79 |
1 |
| others[1] |
6 |
1 |
|
T96 |
1 |
|
T22 |
1 |
|
T45 |
1 |
| others[2] |
8 |
1 |
|
T9 |
1 |
|
T8 |
1 |
|
T73 |
1 |
| others[3] |
18 |
1 |
|
T15 |
1 |
|
T84 |
1 |
|
T92 |
1 |
| false |
4 |
1 |
|
T40 |
1 |
|
T46 |
1 |
|
T120 |
1 |
| true |
37 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T9 |
1 |
|
T105 |
1 |
|
T59 |
1 |
| others[1] |
11 |
1 |
|
T15 |
1 |
|
T72 |
1 |
|
T43 |
1 |
| others[2] |
9 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T76 |
1 |
| others[3] |
10 |
1 |
|
T3 |
1 |
|
T21 |
1 |
|
T63 |
1 |
| false |
7 |
1 |
|
T83 |
1 |
|
T84 |
1 |
|
T94 |
1 |
| true |
34 |
1 |
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T73 |
1 |
|
T46 |
1 |
|
T120 |
1 |
| others[1] |
10 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T84 |
1 |
| others[2] |
11 |
1 |
|
T8 |
1 |
|
T72 |
1 |
|
T76 |
1 |
| others[3] |
16 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T26 |
1 |
| false |
4 |
1 |
|
T1 |
1 |
|
T93 |
1 |
|
T95 |
1 |
| true |
36 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8 |
1 |
|
T96 |
1 |
|
T22 |
1 |
|
T85 |
1 |
| others[1] |
6 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T84 |
1 |
| others[2] |
7 |
1 |
|
T11 |
1 |
|
T72 |
1 |
|
T105 |
1 |
| others[3] |
13 |
1 |
|
T7 |
1 |
|
T12 |
1 |
|
T14 |
1 |
| false |
5 |
1 |
|
T15 |
1 |
|
T26 |
1 |
|
T92 |
1 |
| true |
41 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T63 |
1 |
|
T101 |
1 |
|
T116 |
1 |
| others[1] |
5 |
1 |
|
T96 |
1 |
|
T95 |
1 |
|
T118 |
1 |
| others[2] |
9 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T72 |
1 |
| others[3] |
13 |
1 |
|
T11 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| false |
7 |
1 |
|
T14 |
1 |
|
T84 |
1 |
|
T42 |
1 |
| true |
35 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T11 |
1 |
|
T83 |
1 |
|
T84 |
1 |
| others[1] |
7 |
1 |
|
T21 |
1 |
|
T106 |
1 |
|
T97 |
1 |
| others[2] |
5 |
1 |
|
T3 |
1 |
|
T26 |
1 |
|
T102 |
1 |
| others[3] |
10 |
1 |
|
T2 |
1 |
|
T93 |
1 |
|
T22 |
1 |
| false |
5 |
1 |
|
T12 |
1 |
|
T118 |
1 |
|
T59 |
1 |
| true |
43 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T2 |
1 |
|
T73 |
1 |
|
T94 |
1 |
| others[1] |
7 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T43 |
1 |
| others[2] |
8 |
1 |
|
T84 |
1 |
|
T76 |
1 |
|
T22 |
1 |
| others[3] |
15 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T8 |
1 |
| false |
3 |
1 |
|
T42 |
1 |
|
T111 |
1 |
|
T112 |
1 |
| true |
38 |
1 |
|
T1 |
1 |
|
T11 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T84 |
1 |
|
T58 |
1 |
|
T107 |
1 |
| others[1] |
8 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T96 |
1 |
| others[2] |
8 |
1 |
|
T2 |
1 |
|
T72 |
1 |
|
T79 |
1 |
| others[3] |
11 |
1 |
|
T76 |
1 |
|
T98 |
1 |
|
T118 |
1 |
| false |
4 |
1 |
|
T100 |
1 |
|
T97 |
1 |
|
T114 |
1 |
| true |
43 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T7 |
1 |
|
T12 |
1 |
|
T84 |
1 |
| others[1] |
8 |
1 |
|
T76 |
1 |
|
T79 |
1 |
|
T43 |
1 |
| others[2] |
5 |
1 |
|
T15 |
1 |
|
T92 |
1 |
|
T98 |
1 |
| others[3] |
14 |
1 |
|
T3 |
1 |
|
T72 |
1 |
|
T96 |
1 |
| false |
7 |
1 |
|
T8 |
1 |
|
T14 |
1 |
|
T93 |
1 |
| true |
40 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T11 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |