Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336	1		T1	8		T2	8		T11	1
all_pins[1]	336	1		T1	8		T2	8		T11	1
all_pins[2]	336	1		T1	8		T2	8		T11	1
all_pins[3]	336	1		T1	8		T2	8		T11	1
all_pins[4]	336	1		T1	8		T2	8		T11	1
all_pins[5]	336	1		T1	8		T2	8		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1440	1		T1	33		T2	39		T11	6
values[0x1]	576	1		T1	15		T2	9		T7	7
transitions[0x0=>0x1]	384	1		T1	12		T2	7		T7	6
transitions[0x1=>0x0]	367	1		T1	12		T2	7		T7	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	180	1		T1	6		T2	6		T11	1
all_pins[0]	values[0x1]	156	1		T1	2		T2	2		T7	4
all_pins[0]	transitions[0x0=>0x1]	81	1		T2	2		T7	4		T9	3
all_pins[0]	transitions[0x1=>0x0]	89	1		T1	4		T2	1		T7	1
all_pins[1]	values[0x0]	172	1		T1	2		T2	7		T11	1
all_pins[1]	values[0x1]	164	1		T1	6		T2	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	140	1		T1	5		T2	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	25	1		T2	1		T9	1		T26	1
all_pins[2]	values[0x0]	287	1		T1	7		T2	7		T11	1
all_pins[2]	values[0x1]	49	1		T1	1		T2	1		T9	1
all_pins[2]	transitions[0x0=>0x1]	34	1		T1	1		T9	1		T26	1
all_pins[2]	transitions[0x1=>0x0]	58	1		T1	3		T2	2		T9	3
all_pins[3]	values[0x0]	263	1		T1	5		T2	5		T11	1
all_pins[3]	values[0x1]	73	1		T1	3		T2	3		T9	3
all_pins[3]	transitions[0x0=>0x1]	52	1		T1	3		T2	2		T9	1
all_pins[3]	transitions[0x1=>0x0]	51	1		T1	1		T2	1		T26	2
all_pins[4]	values[0x0]	264	1		T1	7		T2	6		T11	1
all_pins[4]	values[0x1]	72	1		T1	1		T2	2		T9	2
all_pins[4]	transitions[0x0=>0x1]	48	1		T1	1		T2	2		T9	2
all_pins[4]	transitions[0x1=>0x0]	38	1		T1	2		T7	2		T9	3
all_pins[5]	values[0x0]	274	1		T1	6		T2	8		T11	1
all_pins[5]	values[0x1]	62	1		T1	2		T7	2		T9	3
all_pins[5]	transitions[0x0=>0x1]	29	1		T1	2		T7	1		T9	1
all_pins[5]	transitions[0x1=>0x0]	106	1		T1	2		T2	2		T7	2