Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

---

Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	99	99	0	0.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_interval	99	99	0	0.00	100	1	1	0

Summary for Variable read_interval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	99	99	0	0.00

User Defined Bins for read_interval

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
duration[1]	0	1	1
duration[2]	0	1	1
duration[3]	0	1	1
duration[4]	0	1	1
duration[5]	0	1	1
duration[6]	0	1	1
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duration[11]	0	1	1
duration[12]	0	1	1
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duration[19]	0	1	1
duration[20]	0	1	1
duration[21]	0	1	1
duration[22]	0	1	1
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duration[24]	0	1	1
duration[25]	0	1	1
duration[26]	0	1	1
duration[27]	0	1	1
duration[28]	0	1	1
duration[29]	0	1	1
duration[30]	0	1	1
duration[31]	0	1	1
duration[32]	0	1	1
duration[33]	0	1	1
duration[34]	0	1	1
duration[35]	0	1	1
duration[36]	0	1	1
duration[37]	0	1	1
duration[38]	0	1	1
duration[39]	0	1	1
duration[40]	0	1	1
duration[41]	0	1	1
duration[42]	0	1	1
duration[43]	0	1	1
duration[44]	0	1	1
duration[45]	0	1	1
duration[46]	0	1	1
duration[47]	0	1	1
duration[48]	0	1	1
duration[49]	0	1	1
duration[50]	0	1	1
duration[51]	0	1	1
duration[52]	0	1	1
duration[53]	0	1	1
duration[54]	0	1	1
duration[55]	0	1	1
duration[56]	0	1	1
duration[57]	0	1	1
duration[58]	0	1	1
duration[59]	0	1	1
duration[60]	0	1	1
duration[61]	0	1	1
duration[62]	0	1	1
duration[63]	0	1	1
duration[64]	0	1	1
duration[65]	0	1	1
duration[66]	0	1	1
duration[67]	0	1	1
duration[68]	0	1	1
duration[69]	0	1	1
duration[70]	0	1	1
duration[71]	0	1	1
duration[72]	0	1	1
duration[73]	0	1	1
duration[74]	0	1	1
duration[75]	0	1	1
duration[76]	0	1	1
duration[77]	0	1	1
duration[78]	0	1	1
duration[79]	0	1	1
duration[80]	0	1	1
duration[81]	0	1	1
duration[82]	0	1	1
duration[83]	0	1	1
duration[84]	0	1	1
duration[85]	0	1	1
duration[86]	0	1	1
duration[87]	0	1	1
duration[88]	0	1	1
duration[89]	0	1	1
duration[90]	0	1	1
duration[91]	0	1	1
duration[92]	0	1	1
duration[93]	0	1	1
duration[94]	0	1	1
duration[95]	0	1	1
duration[96]	0	1	1
duration[97]	0	1	1
duration[98]	0	1	1
duration[99]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Excluded