Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T1	7		T2	7		T7	4
all_values[1]	281	1		T1	7		T2	7		T7	4
all_values[2]	281	1		T1	7		T2	7		T7	4
all_values[3]	281	1		T1	7		T2	7		T7	4
all_values[4]	281	1		T1	7		T2	7		T7	4
all_values[5]	281	1		T1	7		T2	7		T7	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	900	1		T1	20		T2	25		T7	14
auto[1]	786	1		T1	22		T2	17		T7	10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	557	1		T1	13		T2	17		T7	9
auto[1]	1129	1		T1	29		T2	25		T7	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1017	1		T1	24		T2	25		T7	18
auto[1]	669	1		T1	18		T2	17		T7	6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	85	1		T1	3		T2	2		T9	2
all_values[0]	auto[0]	auto[1]	auto[1]	80	1		T1	1		T7	3		T9	3
all_values[0]	auto[1]	auto[0]	auto[1]	68	1		T1	2		T2	4		T9	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T1	1		T2	1		T7	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1		T1	2		T2	2		T7	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1		T1	3		T2	2		T9	1
all_values[1]	auto[1]	auto[0]	auto[1]	56	1		T2	3		T7	1		T9	2
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T1	2		T9	1		T8	1
all_values[2]	auto[0]	auto[0]	auto[0]	89	1		T1	2		T2	2		T9	3
all_values[2]	auto[0]	auto[1]	auto[0]	90	1		T1	1		T2	3		T7	4
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T1	3		T2	2		T9	1
all_values[2]	auto[1]	auto[1]	auto[1]	42	1		T1	1		T9	2		T26	1
all_values[3]	auto[0]	auto[0]	auto[0]	75	1		T1	1		T7	4		T8	1
all_values[3]	auto[0]	auto[1]	auto[0]	72	1		T1	2		T2	2		T9	1
all_values[3]	auto[1]	auto[0]	auto[1]	85	1		T1	1		T2	5		T9	4
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T1	3		T9	2		T8	1
all_values[4]	auto[0]	auto[0]	auto[0]	61	1		T1	3		T2	1		T8	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1		T7	2		T9	2		T8	1
all_values[4]	auto[0]	auto[1]	auto[0]	52	1		T1	2		T2	4		T9	2
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T2	1		T26	1		T83	1
all_values[4]	auto[1]	auto[0]	auto[1]	48	1		T2	1		T7	2		T8	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T1	2		T9	3		T8	1
all_values[5]	auto[0]	auto[0]	auto[0]	68	1		T2	2		T7	1		T9	2
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T1	1		T2	1		T9	1
all_values[5]	auto[0]	auto[1]	auto[0]	50	1		T1	2		T2	3		T84	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T1	1		T7	1		T9	1
all_values[5]	auto[1]	auto[0]	auto[1]	50	1		T1	2		T7	1		T83	1
all_values[5]	auto[1]	auto[1]	auto[1]	60	1		T1	1		T2	1		T7	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal