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 LINE       12224
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T59
1	1	1	Covered	T1,T2,T3

 LINE       12239
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T60
1	1	1	Covered	T1,T2,T3

 LINE       12254
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T55,T56,T60
1	1	1	Covered	T1,T2,T3

 LINE       12269
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T22,T59
1	1	1	Covered	T1,T2,T3

 LINE       12274
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T14,T15
1	1	1	Covered	T1,T2,T3

 LINE       12279
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T18,T59
1	1	1	Covered	T1,T2,T3

 LINE       12284
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T5,T14
1	1	1	Covered	T1,T2,T3

 LINE       12289
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T14,T15
1	1	1	Covered	T1,T2,T3

 LINE       12294
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T22,T59
1	1	1	Covered	T1,T2,T3

 LINE       12299
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T1,T2,T3

 LINE       12304
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T55,T64
1	1	1	Covered	T1,T2,T3

 LINE       12309
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T1,T2,T3

 LINE       12322
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T4,T5,T10

 LINE       12325
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T14,T59
1	1	1	Covered	T4,T5,T10

 LINE       12328
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T15,T63
1	1	1	Covered	T4,T5,T10

 LINE       12331
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T4,T12,T14
1	1	1	Covered	T4,T5,T10

 LINE       12334
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T15,T63
1	1	1	Covered	T4,T5,T10

 LINE       12337
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T4,T12,T22
1	1	1	Covered	T4,T5,T10

 LINE       12340
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T65,T22,T59
1	1	1	Covered	T4,T5,T10

 LINE       12343
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T63,T59,T55
1	1	1	Covered	T4,T5,T10

 LINE       12346
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T5,T14
1	1	1	Covered	T4,T5,T10

 LINE       12349
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T14,T55,T56
1	1	1	Covered	T4,T5,T10

 LINE       12352
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T1,T2,T3

 LINE       12367
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T1,T2,T3

 LINE       12382
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T63
1	1	1	Covered	T1,T2,T3

 LINE       12397
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T22,T55
1	1	1	Covered	T1,T2,T3

 LINE       12412
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T22,T59
1	1	1	Covered	T1,T2,T3

 LINE       12427
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T15,T22
1	1	1	Covered	T1,T2,T3

 LINE       12442
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T1,T2,T3

 LINE       12457
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T22,T63
1	1	1	Covered	T1,T2,T3

 LINE       12472
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T66
1	1	1	Covered	T1,T2,T3

 LINE       12487
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T59,T60,T67
1	1	1	Covered	T1,T2,T3

 LINE       12502
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T59,T55
1	1	1	Covered	T4,T5,T10

 LINE       12505
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T22,T55
1	1	1	Covered	T1,T2,T3

 LINE       12520
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T59
1	1	1	Covered	T4,T5,T10

 LINE       12523
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T4,T5,T10

 LINE       12526
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T15,T22
1	1	1	Covered	T1,T2,T3

 LINE       12541
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T59
1	1	1	Covered	T1,T2,T3

 LINE       12556
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T59,T55
1	1	1	Covered	T4,T5,T10

 LINE       12559
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T63
1	1	1	Covered	T4,T5,T10

 LINE       12562
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T57,T55
1	1	1	Covered	T4,T5,T10

 LINE       12565
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T4,T5,T10

 LINE       12568
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T14,T22,T55
1	1	1	Covered	T4,T5,T10

 LINE       12571
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T14,T23
1	1	1	Covered	T4,T5,T10

 LINE       12574
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T55,T58
1	1	1	Covered	T4,T5,T10

 LINE       12577
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T58
1	1	1	Covered	T4,T5,T10

 LINE       12580
 EXPRESSION (addr_hit[71] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T4,T5,T10

 LINE       12583
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T15,T22,T63
1	1	1	Covered	T4,T5,T10

 LINE       12586
 EXPRESSION (addr_hit[73] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T55
1	1	1	Covered	T1,T2,T3

 LINE       12601
 EXPRESSION (addr_hit[74] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T18,T55,T64
1	1	1	Covered	T1,T2,T3

 LINE       12616
 EXPRESSION (addr_hit[75] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T22,T56
1	1	1	Covered	T1,T2,T3

 LINE       12631
 EXPRESSION (addr_hit[76] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T55,T64
1	1	1	Covered	T1,T2,T3

 LINE       12646
 EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T18,T55
1	1	1	Covered	T1,T2,T3

 LINE       12661
 EXPRESSION (addr_hit[78] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T6,T14
1	1	1	Covered	T1,T2,T3

 LINE       12676
 EXPRESSION (addr_hit[79] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T22,T55
1	1	1	Covered	T1,T2,T3

 LINE       12691
 EXPRESSION (addr_hit[80] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T63,T55
1	1	1	Covered	T1,T2,T3

 LINE       12706
 EXPRESSION (addr_hit[81] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T1,T2,T3

 LINE       12721
 EXPRESSION (addr_hit[82] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T22,T56
1	1	1	Covered	T1,T2,T3

 LINE       12736
 EXPRESSION (addr_hit[83] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T15,T59,T55
1	1	1	Covered	T4,T5,T10

 LINE       12739
 EXPRESSION (addr_hit[84] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T55,T58,T64
1	1	1	Covered	T1,T2,T3

 LINE       12754
 EXPRESSION (addr_hit[85] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T22,T63,T55
1	1	1	Covered	T4,T5,T10

 LINE       12757
 EXPRESSION (addr_hit[86] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T12
1	1	0	Covered	T14,T22,T59
1	1	1	Covered	T4,T5,T10

 LINE       12760
 EXPRESSION (addr_hit[87] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T14,T55
1	1	1	Covered	T1,T2,T3

 LINE       12775
 EXPRESSION (addr_hit[88] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T55,T68
1	1	1	Covered	T1,T2,T3

 LINE       12790
 EXPRESSION (addr_hit[89] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T4,T5,T10

 LINE       12795
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T12
1	1	0	Covered	T12,T58,T64
1	1	1	Covered	T4,T5,T10

 LINE       12798
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T62
1	1	1	Covered	T4,T5,T10

 LINE       12799
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T15,T58,T60
1	1	1	Covered	T4,T5,T10

 LINE       12804
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T14,T63,T58
1	1	1	Covered	T4,T5,T10

 LINE       12809
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T10

 LINE       12810
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T12
1	1	0	Covered	T14,T15,T22
1	1	1	Covered	T4,T5,T10

 LINE       12827
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T12,T14,T22
1	1	1	Covered	T4,T5,T10

 LINE       12832
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T12
1	1	0	Covered	T14,T22,T59
1	1	1	Not Covered

 LINE       12837
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T63,T55
1	1	1	Covered	T4,T5,T10

 LINE       12840
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T61,T58,T64
1	1	1	Covered	T4,T5,T10

 LINE       12845
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T4,T7
1	1	0	Covered	T12,T14,T66
1	1	1	Covered	T4,T5,T10

 LINE       12848
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T4
1	1	0	Covered	T66
1	1	1	Covered	T4,T5,T10

 LINE       13709
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3