FLASH_CTRL Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.687m	55.655us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.160s	16.169us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	44.880s	99.369us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.353m	4.483ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.194m	1.791ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.530s	277.247us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.194m	1.791ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.530s	14.074us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.710s	44.912us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.570s	24.102us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.865m	62.337us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	39.612m	480.631ms	3	3	100.00
		flash_ctrl_hw_rma_reset	24.786m	760.583ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.870s	15.517us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.513m	260.092ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.434m	6.838ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	21.220s	436.728us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.159h	113.478ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.519m	1.467ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.360s	412.701us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.230s	196.836us	40	40	100.00
		flash_ctrl_re_evict	40.190s	141.100us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.075m	4.727ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.075m	4.727ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.335m	100.284ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	26.730s	217.353us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.953m	1.717ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.049m	7.198ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.822m	1.864ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.853m	4.113ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.880s	19.070us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.410m	6.885ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.720s	49.928us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.460s	16.799us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.193m	1.061ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.438m	24.289ms	50	50	100.00
		flash_ctrl_otp_reset	2.303m	199.491us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	39.612m	480.631ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.250m	4.979ms	40	40	100.00
		flash_ctrl_intr_wr	2.590m	58.744ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.541m	27.294ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.767m	469.333ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.657m	3.889ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.308m	1.337ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.930s	33.175us	5	5	100.00
		flash_ctrl_ro_derr	3.158m	1.991ms	10	10	100.00
		flash_ctrl_rw_derr	12.243m	16.490ms	10	10	100.00
		flash_ctrl_derr_detect	1.743m	188.937us	5	5	100.00
		flash_ctrl_integrity	10.050m	34.925ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.580s	26.463us	5	5	100.00
		flash_ctrl_ro_serr	2.686m	3.245ms	10	10	100.00
		flash_ctrl_rw_serr	13.236m	4.989ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.298m	632.291us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.408m	1.331ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.314m	50.822ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.020s	166.609us	1	1	100.00
		flash_ctrl_read_word_sweep	14.980s	26.233us	1	1	100.00
		flash_ctrl_ro	2.189m	2.240ms	20	20	100.00
		flash_ctrl_rw	11.940m	20.270ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.660s	575.809us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	23.232m	86.759ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.677m	10.016ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.280s	38.787us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.200s	41.311us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.620s	1.101ms	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.620s	1.101ms	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	44.880s	99.369us	5	5	100.00
		flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.194m	1.791ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	839.882us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	44.880s	99.369us	5	5	100.00
		flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.194m	1.791ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	839.882us	20	20	100.00
V2		TOTAL			1012	1013	99.90
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.950s	18.468us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.965m	729.436us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.965m	729.436us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.965m	729.436us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.790s	217.050us	3	3	100.00
		flash_ctrl_wr_intg	14.480s	43.809us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.687m	55.655us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.303m	199.491us	80	80	100.00
		flash_ctrl_disable	22.720s	49.928us	50	50	100.00
		flash_ctrl_sec_info_access	1.734m	25.912ms	50	50	100.00
		flash_ctrl_connect	16.460s	16.799us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.140s	138.512us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.160s	1.053ms	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.940s	33.177us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.720s	49.928us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.790s	217.050us	3	3	100.00
		flash_ctrl_access_after_disable	14.090s	42.195us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.720s	49.928us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.730s	217.353us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.940m	20.270ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.236m	4.989ms	10	10	100.00
		flash_ctrl_rw_derr	12.243m	16.490ms	10	10	100.00
		flash_ctrl_integrity	10.050m	34.925ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	39.612m	480.631ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.198m	685.703us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.640s	90.365us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.870s	198.366us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.325h	1.963ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.010s	84.047us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1277	1278	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.52	95.76	94.15	98.85	92.52	98.16	98.01	98.21

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
  • Test flash_ctrl_lcmgr_intg has 1 failures.

    • 12.flash_ctrl_lcmgr_intg.30743209197466324069354016199871763823840146340740875516709198400580708483664
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 14069.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 14069.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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