Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total995010
Category 0995010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total995010
Severity 0995010

Summary for Assertions
NUMBERPERCENT
Total Number995100.00
Uncovered171.71
Success97898.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00435599635458607800
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 004355996353604873900
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004355996353604873900
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00435599635583456600
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00435599635583456600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 004355996353479595700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004355996353479595700
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001062106200
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0042981353542894302400
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0042981353542894302400
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_tl_gate.u_state_regs_A 0043559963543472912400
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001062106200
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001062106200
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001062106200
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001062106200
tb.dut.u_to_prog_fifo.TlOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A 00435599635358191300
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable 0043559963543472912400
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.WeOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001062106200
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00435599635358191300
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00435599635358191300
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001062106200
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001062106200
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001062106200
tb.dut.u_to_rd_fifo.TlOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A 00435599635488433500
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable 0043559963543472912400
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.WeOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001062106200
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00435599635329801500
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00435017703329141800
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00435599635488433500
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00435599635488433500
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00435432772487688800
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00435599635489019300
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00435599635329801500
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0043559963543472912400
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00435599635329801500

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004355996352996501056
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004355996352729301056
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0042981353542890886302778
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00435599635001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00435599635001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00435599635001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00435599635001056
tb.dut.u_flash_hw_if.DisableChk_A 004236028957569313043
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0042981371042890902302778
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0042978978942888525202628
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0042981371042890902302778
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0042981371042890902302778
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0042981371042890902302778
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0042981371042890902302778
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0042981371042890902302778

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00438427438000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00438427438000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00438427438000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0043842743888775887750
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0043842743815150
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00438427438990
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00438427438770
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0043842743820888208880
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004384274383011843011840
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0043842743816826523168265231251

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0043842743888775887750
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0043842743815150
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00438427438990
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00438427438770
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0043842743820888208880
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004384274383011843011840
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0043842743816826523168265231251