Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered171.71
Success97598.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001061106100
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 004147155063546811600
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004147155063546811600
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001061106100
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001061106100
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00414715506517734500
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414715506517734500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 004147155063483441500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004147155063483441500
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0040864886340780747300
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0040864886340780747300
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001061106100
tb.dut.u_tl_gate.u_state_regs_A 0041471550641387411600
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001061106100
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001061106100
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001061106100
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001061106100
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001061106100
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.TlOutValidKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.WeOutKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001061106100
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001061106100
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00414715506355401600
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414715506355401600
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001061106100
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001061106100
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001061106100
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001061106100
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001061106100
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.TlOutValidKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.WeOutKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001061106100
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00414715506325418500
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00413863637324773600
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001061106100
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00414715506488798200
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414715506488798200
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001061106100
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001061106100
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00414404948488340400
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414715506489986000
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00414715506325418500
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414715506325418500

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004147155062951701055
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004147155062580201055
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0040864886340777453602775
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00414715506001055
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00414715506001055
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00414715506001055
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00414715506001055
tb.dut.u_flash_hw_if.DisableChk_A 004022318117141105046
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0040862660840775241602625
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00417238156000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00417238156000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00417238156000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0041723815682313823130
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0041723815611110
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00417238156550
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00417238156220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0041723815610853108530
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004172381562834872834870
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0041723815622488703224887031250

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0041723815682313823130
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0041723815611110
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00417238156550
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00417238156220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0041723815610853108530
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004172381562834872834870
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0041723815622488703224887031250