Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered171.71
Success97598.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A 004144049481274098400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004144049481274098400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A 004144049484985061100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004144049484985061100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A 0041471550641387411600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A 001061106100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A 00414715506268288700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A 00414715506268288700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A 0041471550641387411600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A 0041471550641387411600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A 00414715506268288700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A 0041471550630851705000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A 00414715506268288700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A 00414715506268288700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A 0041471550610075972200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004147155062580201055
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A 0041471550641387411600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A 001061106100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A 0041471550641387411600
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A 00414404948306126300
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A 0041440494841356355800
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00414404948306126300
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A 004147155063483441500
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A 0041471550641387411600
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004147155063483441500
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A 0041471550641387411600
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004147155062362597800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00414715506692086500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00414715506714642200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 0041471550611346750900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0041471550611346750900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004147155067441427800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00414715506726160200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00414715506605551800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00414715506609179800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 004147155068911648000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004147155068911648000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001061106100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004147155066871336600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit 004172374486368200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv 004172374486368200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse 004172374484435300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck 001276127600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse 004172374481932900
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A 0040864886340780747300
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0040864886340777453602775
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A 001061106100
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.StagePow2_A 001061106100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001061106100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 004147154281640403700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041471550638106592200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004147155063280808200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004146756871640387900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004147155061640403500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001061106100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 004147154281640403700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041471550638106588300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004147155063280815900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004146756871640387900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004147155061640407300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001061106100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 004146720051586837700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041471550638213718700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004147155063173685100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004145994661586834500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004147155061586842100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001061106100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 004147155061586849800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 004147155061586849800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004147155061586849800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 004146720051586837700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041471550638213710900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004147155061586849800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004147155061586849800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004147155063173700600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004145994661586834500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0041471550641387411600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004147155061586849800
tb.dut.u_flash_hw_if.DisableChk_A 004022318117141105046
tb.dut.u_flash_hw_if.ProgRdVerify_A 00399544488204354100
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq 00414715532923900
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq 00414619815890300
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq 00414715532919800
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq 00403595452890800
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A 001061106100
tb.dut.u_flash_hw_if.u_rma_state_regs_A 0041471553241387414200
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A 001061106100
tb.dut.u_flash_hw_if.u_state_regs_A 0041471553241387414200
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A 0040864888940780749900
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_flash_mp.BankEraseData_A 00414715532740695800
tb.dut.u_flash_mp.BankEraseInfo_A 004147155321291138000
tb.dut.u_flash_mp.DataReqToInfo_A 0041471553227112100200
tb.dut.u_flash_mp.InReqOutReq_A 0041471553230792410600
tb.dut.u_flash_mp.InfoReqToData_A 004147155323680310400
tb.dut.u_flash_mp.NoReqWhenErr_A 0040778604310776000
tb.dut.u_flash_mp.bkEraseEnOnehot_A 004147155322031833800
tb.dut.u_flash_mp.hwInfoRuleOnehot_A 0041471553215542114900
tb.dut.u_flash_mp.invalidReqOnehot_A 0041471553230781630300
tb.dut.u_flash_mp.requestTypesOnehot_A 0041471553230781630300
tb.dut.u_intr_corr_err.IntrTKind_A 001061106100
tb.dut.u_intr_op_done.IntrTKind_A 001061106100
tb.dut.u_intr_prog_empty.IntrTKind_A 001061106100
tb.dut.u_intr_prog_lvl.IntrTKind_A 001061106100
tb.dut.u_intr_rd_full.IntrTKind_A 001061106100
tb.dut.u_intr_rd_lvl.IntrTKind_A 001061106100
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A 0040862660840778521800
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0040862660840775241602625
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A 0040864888940780749900
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_prog_fifo.DataKnown_A 0041471550619707940600
tb.dut.u_prog_fifo.DepthKnown_A 0041471550641387411600
tb.dut.u_prog_fifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_prog_fifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0041471550619707940600
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A 0040864886340780747300
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0040864886340780747300
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A 001061106100
tb.dut.u_prog_tl_gate.u_state_regs_A 0041471550641387411600
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001061106100
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001061106100
tb.dut.u_reg_core.en2addrHit 004172374742951271200
tb.dut.u_reg_core.reAfterRv 004172374742951269900
tb.dut.u_reg_core.rePulse 004172374742717186500
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001276127600
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A 001276127600
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A 0041723747441631100300
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A 001276127600
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A 0041723747441631100300
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001276127600
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001276127600
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001276127600
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001276127600
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001276127600
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001276127600
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001276127600
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 004172374483638383600
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 004172374484582401200
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 00417237448235665200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 00417237448357302800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00417237448408265100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00417237448489145200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 004172374482987643900
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 004172374483735953200
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 0041723744841631097700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001276127600
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001276127600
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001276127600
tb.dut.u_reg_core.u_socket.maxN 001276127600
tb.dut.u_reg_core.wePulse 00417237474234083400
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001061106100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041471553241387414200
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A 0040864888940780749900
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A 0040864888940780749900
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A 0040864888940780749900
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001061106100
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A 0040864888940780749900
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040864888940777454702775
tb.dut.u_sw_rd_fifo.DataKnown_A 004147155064876699100
tb.dut.u_sw_rd_fifo.DepthKnown_A 0041471550641387411600
tb.dut.u_sw_rd_fifo.RvalidKnown_A 0041471550641387411600
tb.dut.u_sw_rd_fifo.WreadyKnown_A 0041471550641387411600
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004147155064876699100
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A 001061106100
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A 001061106100
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A 001061106100
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.WeOutKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A 0041471550641387411600
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite 001061106100
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck 001061106100
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty 00414715506454813700
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00414715506454813700
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