Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered515.14
Success94194.86
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered220.00
All Matches880.00
First Matches880.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A 003639732041216234000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth 003639732041216234000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A 003639732044757199400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003639732044757199400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A 0087387300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A 00363973204223119200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A 00363973204223119200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A 00363973204223119200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A 0036397320425744811100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A 00363973204223119200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A 00363973204223119200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A 0036397320410130538000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 0036397320431610868
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A 0087387300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A 00363973204207584300
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00363973204207584300
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A 003639732043011392300
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003639732043011392300
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A 0036397320436329825500
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 003639732041195061000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00363973204487552000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00363973204492481200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 003639732047483780600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003639732047483780600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 003639732044966891700
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00363973204764927600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00363973204646092800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00363973204650676400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 003639732047197446700
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003639732047197446700
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 0087387300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 003639732045363888200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit 003664719666712200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv 003664719666712200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse 003664719664680000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck 001088108800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse 003664719662032200
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A 0035827827135760332200
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0035827827135757689202214
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A 0087387300
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.StagePow2_A 0087387300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 0087387300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 003639729711670619900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036397320432988570000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003639732043341247300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003637744591670563800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003639732041670619800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 0087387300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 003639729711670619900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036397320432988568200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003639732043341257300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003637744591670563800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003639732041670628000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 0087387300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 003639731141500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036397320433327820100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003639732043002005400
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003639560131500994300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 0087387300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 003639731141500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036397320433327828800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003639732041500998300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003639732043001996700
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003639560131500994300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0036397320436329825500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003639732041500998300
tb.dut.u_flash_hw_if.DisableChk_A 003520809324714408032
tb.dut.u_flash_hw_if.ProgRdVerify_A 00348888031204353700
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq 00363973350878400
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq 00363878800845200
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq 00363973350875300
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq 00347485450845300
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A 0087387300
tb.dut.u_flash_hw_if.u_rma_state_regs_A 0036397335036329840100
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A 0087387300
tb.dut.u_flash_hw_if.u_state_regs_A 0036397335036329840100
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A 0035827841735760346800
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_flash_mp.BankEraseData_A 00363973350924268500
tb.dut.u_flash_mp.BankEraseInfo_A 003639733501127288000
tb.dut.u_flash_mp.DataReqToInfo_A 0036397335022518838900
tb.dut.u_flash_mp.InReqOutReq_A 0036397335024929268800
tb.dut.u_flash_mp.InfoReqToData_A 003639733502410429900
tb.dut.u_flash_mp.NoReqWhenErr_A 0035914572510665400
tb.dut.u_flash_mp.bkEraseEnOnehot_A 003639733502051556500
tb.dut.u_flash_mp.hwInfoRuleOnehot_A 0036397335015558233600
tb.dut.u_flash_mp.invalidReqOnehot_A 0036397335024918599700
tb.dut.u_flash_mp.requestTypesOnehot_A 0036397335024918599700
tb.dut.u_intr_corr_err.IntrTKind_A 0087387300
tb.dut.u_intr_op_done.IntrTKind_A 0087387300
tb.dut.u_intr_prog_empty.IntrTKind_A 0087387300
tb.dut.u_intr_prog_lvl.IntrTKind_A 0087387300
tb.dut.u_intr_rd_full.IntrTKind_A 0087387300
tb.dut.u_intr_rd_lvl.IntrTKind_A 0087387300
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A 0035826260135758765200
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0035826260135756131202109
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A 0035827841735760346800
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_prog_fifo.DataKnown_A 0036397320413677213500
tb.dut.u_prog_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_prog_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_prog_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0036397320413677213500
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A 0035827827135760332200
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0035827827135760332200
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A 0087387300
tb.dut.u_prog_tl_gate.u_state_regs_A 0036397320436329825500
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 0087387300
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 0087387300
tb.dut.u_reg_core.en2addrHit 003664721122118017700
tb.dut.u_reg_core.reAfterRv 003664721122118017400
tb.dut.u_reg_core.rePulse 003664721121909353600
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001088108800
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A 001088108800
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A 0036647211236570322700
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A 001088108800
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A 0036647211236570322700
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001088108800
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001088108800
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001088108800
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001088108800
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001088108800
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001088108800
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001088108800
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 003664719662726607500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 003664719663933455700
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 00366471966195386300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 00366471966361933700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00366471966389665500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00366471966525469300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 003664719662139371200
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 003664719663046052700
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 0036647196636570308100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001088108800
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001088108800
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001088108800
tb.dut.u_reg_core.u_socket.maxN 001088108800
tb.dut.u_reg_core.wePulse 00366472112208663800
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 0087387300
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036397335036329840100
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A 0035827841735760346800
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A 0035827841735760346800
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A 0035827841735760346800
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A 0035827841735760346800
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035827841735757702302214
tb.dut.u_sw_rd_fifo.DataKnown_A 003639732045369178600
tb.dut.u_sw_rd_fifo.DepthKnown_A 0036397320436329825500
tb.dut.u_sw_rd_fifo.RvalidKnown_A 0036397320436329825500
tb.dut.u_sw_rd_fifo.WreadyKnown_A 0036397320436329825500
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003639732045369178600
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A 0087387300
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A 0087387300
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A 0087387300
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.WeOutKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A 0036397320436329825500
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite 0087387300
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck 0087387300
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty 00363973204345485600
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00363973204345485600
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