GPIO Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.550s	159.795us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.650s	406.255us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.640s	16.740us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	18.588us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.980s	82.776us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	32.603us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.400s	54.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	18.588us	20	20	100.00
		gpio_csr_aliasing	0.870s	32.603us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.310s	69.172us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	113.774us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	44.259us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.420s	229.109us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.670s	121.976us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.830s	481.465us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	25.750s	649.235us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.950s	264.814us	50	50	100.00
V2	full_random	gpio_full_random	1.130s	372.054us	50	50	100.00
V2	stress_all	gpio_stress_all	3.669m	79.954ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.610s	14.168us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	96.944us	22	50	44.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.520s	1.399ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.520s	1.399ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	18.588us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	33.723us	20	20	100.00
		gpio_csr_aliasing	0.870s	32.603us	5	5	100.00
		gpio_csr_hw_reset	0.640s	16.740us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	18.588us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	33.723us	20	20	100.00
		gpio_csr_aliasing	0.870s	32.603us	5	5	100.00
		gpio_csr_hw_reset	0.640s	16.740us	5	5	100.00
V2		TOTAL			612	640	95.62
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	130.579us	20	20	100.00
		gpio_sec_cm	1.080s	320.126us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	130.579us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.664m	610.399ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			842	870	96.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 28 failures:

Test gpio_intr_test has 28 failures.

3.gpio_intr_test.3507271367
Line 219, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest/run.log

  UVM_ERROR @   5972904 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3838791589 [0xe4cf4fa5]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   5972904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.gpio_intr_test.3809090754
Line 221, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/5.gpio_intr_test/latest/run.log

  UVM_ERROR @  10493760 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 1068332027 [0x3fad73fb]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @  10493760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.