V1 |
smoke |
gpio_smoke |
1.450s |
363.119us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown |
1.480s |
409.656us |
50 |
50 |
100.00 |
|
|
gpio_smoke_en_cdc_prim |
1.480s |
197.675us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown_en_cdc_prim |
1.470s |
93.359us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
gpio_csr_hw_reset |
0.660s |
68.970us |
5 |
5 |
100.00 |
V1 |
csr_rw |
gpio_csr_rw |
0.630s |
30.342us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
gpio_csr_bit_bash |
2.460s |
1.004ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
gpio_csr_aliasing |
0.790s |
116.355us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
gpio_csr_mem_rw_with_rand_reset |
1.460s |
137.783us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
gpio_csr_rw |
0.630s |
30.342us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.790s |
116.355us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
255 |
255 |
100.00 |
V2 |
direct_and_masked_out |
gpio_random_dout_din |
1.450s |
75.442us |
50 |
50 |
100.00 |
|
|
gpio_random_dout_din_no_pullup_pulldown |
1.280s |
66.011us |
50 |
50 |
100.00 |
V2 |
out_in_regs_read_write |
gpio_dout_din_regs_random_rw |
0.990s |
41.482us |
50 |
50 |
100.00 |
V2 |
gpio_interrupt_programming |
gpio_intr_rand_pgm |
1.420s |
86.525us |
50 |
50 |
100.00 |
V2 |
random_interrupt_trigger |
gpio_rand_intr_trigger |
3.500s |
809.455us |
50 |
50 |
100.00 |
V2 |
interrupt_and_noise_filter |
gpio_intr_with_filter_rand_intr_event |
3.680s |
623.380us |
50 |
50 |
100.00 |
V2 |
noise_filter_stress |
gpio_filter_stress |
27.970s |
3.162ms |
50 |
50 |
100.00 |
V2 |
regs_long_reads_and_writes |
gpio_random_long_reg_writes_reg_reads |
6.620s |
2.861ms |
50 |
50 |
100.00 |
V2 |
full_random |
gpio_full_random |
1.110s |
611.270us |
50 |
50 |
100.00 |
V2 |
stress_all |
gpio_stress_all |
3.580m |
150.902ms |
50 |
50 |
100.00 |
V2 |
alert_test |
gpio_alert_test |
0.640s |
20.412us |
50 |
50 |
100.00 |
V2 |
intr_test |
gpio_intr_test |
0.630s |
22.544us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
gpio_tl_errors |
2.920s |
141.760us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
gpio_tl_errors |
2.920s |
141.760us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
gpio_csr_rw |
0.630s |
30.342us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.860s |
166.434us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.790s |
116.355us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.660s |
68.970us |
5 |
5 |
100.00 |
V2 |
tl_d_partial_access |
gpio_csr_rw |
0.630s |
30.342us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.860s |
166.434us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.790s |
116.355us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.660s |
68.970us |
5 |
5 |
100.00 |
V2 |
|
TOTAL |
|
|
640 |
640 |
100.00 |
V2S |
tl_intg_err |
gpio_tl_intg_err |
1.420s |
127.346us |
20 |
20 |
100.00 |
|
|
gpio_sec_cm |
0.890s |
258.184us |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
gpio_tl_intg_err |
1.420s |
127.346us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
V3 |
stress_all_with_rand_reset |
gpio_stress_all_with_rand_reset |
48.192m |
229.911ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
970 |
970 |
100.00 |