HMAC Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.460s	1.604ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.720s	203.810us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.750s	25.150us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.890s	876.155us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.440s	352.886us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.834m	583.275ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.750s	25.150us	20	20	100.00
		hmac_csr_aliasing	2.440s	352.886us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.425m	7.573ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	52.080s	2.161ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.955m	47.145ms	48	50	96.00
		hmac_test_hmac_vectors	1.180s	72.705us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.426m	1.897ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.590m	6.151ms	50	50	100.00
V2	error	hmac_error	3.926m	57.069ms	49	50	98.00
V2	wipe_secret	hmac_wipe_secret	1.272m	53.986ms	50	50	100.00
V2	stress_all	hmac_stress_all	46.236m	839.250ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	14.780us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	94.929us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.550s	802.275us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.550s	802.275us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.720s	203.810us	5	5	100.00
		hmac_csr_rw	0.750s	25.150us	20	20	100.00
		hmac_csr_aliasing	2.440s	352.886us	5	5	100.00
		hmac_same_csr_outstanding	1.390s	83.090us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.720s	203.810us	5	5	100.00
		hmac_csr_rw	0.750s	25.150us	20	20	100.00
		hmac_csr_aliasing	2.440s	352.886us	5	5	100.00
		hmac_same_csr_outstanding	1.390s	83.090us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	1.140s	190.427us	5	5	100.00
		hmac_tl_intg_err	2.490s	180.845us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.490s	180.845us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.460s	1.604ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.657h	166.869ms	190	200	95.00
V3		TOTAL			190	200	95.00
		TOTAL			907	920	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.54	98.47	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 8 failures:

Test hmac_stress_all_with_rand_reset has 8 failures.

0.hmac_stress_all_with_rand_reset.1968355129
Line 538, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16612324414 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16612324414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.hmac_stress_all_with_rand_reset.1421300116
Line 306, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20174818274 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 20174818274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test hmac_test_sha_vectors has 2 failures.

16.hmac_test_sha_vectors.3492841866
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.hmac_test_sha_vectors.2034066086
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test hmac_error has 1 failures.

30.hmac_error.1456829463
Line 256, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/30.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 8.hmac_stress_all_with_rand_reset.3922256178
    Line 593, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35096813764 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 35096813764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 127.hmac_stress_all_with_rand_reset.632428848
    Line 684, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/127.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 136083580247 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 136083580247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```