HMAC Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.210s	1.240ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.760s	26.367us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.790s	13.642us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.970s	5.284ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.360s	113.327us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	22.599m	431.752ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.790s	13.642us	20	20	100.00
		hmac_csr_aliasing	2.360s	113.327us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.664m	8.904ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	58.080s	6.526ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.323m	84.989ms	50	50	100.00
		hmac_test_hmac_vectors	1.300s	277.676us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.160m	1.743ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.352m	13.851ms	50	50	100.00
V2	error	hmac_error	3.880m	59.021ms	48	50	96.00
V2	wipe_secret	hmac_wipe_secret	1.384m	13.953ms	50	50	100.00
V2	stress_all	hmac_stress_all	40.696m	236.162ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.730s	49.206us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	16.955us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.910s	208.182us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.910s	208.182us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.760s	26.367us	5	5	100.00
		hmac_csr_rw	0.790s	13.642us	20	20	100.00
		hmac_csr_aliasing	2.360s	113.327us	5	5	100.00
		hmac_same_csr_outstanding	1.500s	136.241us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.760s	26.367us	5	5	100.00
		hmac_csr_rw	0.790s	13.642us	20	20	100.00
		hmac_csr_aliasing	2.360s	113.327us	5	5	100.00
		hmac_same_csr_outstanding	1.500s	136.241us	20	20	100.00
V2		TOTAL			588	590	99.66
V2S	tl_intg_err	hmac_sec_cm	1.050s	112.629us	5	5	100.00
		hmac_tl_intg_err	2.320s	482.226us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.320s	482.226us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.210s	1.240ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.715h	146.643ms	195	200	97.50
V3		TOTAL			195	200	97.50
		TOTAL			913	920	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.53	98.47	100.00	100.00	99.76	99.49	99.86

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:
  • Test hmac_stress_all_with_rand_reset has 5 failures.

    • 45.hmac_stress_all_with_rand_reset.100747416979146993778607174771945568582165273233383057720227072372187074199709
      Line 813, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51689291672 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 51689291672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 104.hmac_stress_all_with_rand_reset.87444006513358606461597468035553400819992269662586299130600330134921666258184
      Line 1342, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/104.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 81678253574 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 81678253574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test hmac_error has 2 failures.

    • 8.hmac_error.28061421242848806507693962957145075119599110331242377535398891502367081657779
      Line 296, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.hmac_error.3417188066086038142319533200013239848077166154344248631175357622738571279398
      Line 294, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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