Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	393548241	2477146	0	0
intr_enable_rd_A	393548241	2020	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393548241	2477146	0	0
T4	155066	0	0	0
T7	169193	75017	0	0
T13	1123	0	0	0
T14	1198	0	0	0
T16	721194	0	0	0
T19	0	49856	0	0
T20	0	22435	0	0
T38	0	388441	0	0
T39	0	80335	0	0
T40	0	120181	0	0
T60	0	5529	0	0
T61	0	54015	0	0
T62	0	66632	0	0
T63	0	62542	0	0
T64	266637	0	0	0
T65	78811	0	0	0
T66	70737	0	0	0
T67	17726	0	0	0
T68	12294	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393548241	2020	0	0
T5	185579	32	0	0
T6	423710	0	0	0
T15	921	0	0	0
T23	8121	0	0	0
T28	335555	0	0	0
T29	73317	0	0	0
T30	5050	0	0	0
T31	32724	0	0	0
T32	306846	0	0	0
T33	1005	0	0	0
T62	0	76	0	0
T69	0	2	0	0
T70	0	19	0	0
T71	0	51	0	0
T72	0	6	0	0
T73	0	17	0	0
T74	0	20	0	0
T75	0	12	0	0
T76	0	64	0	0