Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.24	94.90	77.89	100.00	40.00	86.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	84.28	94.90	84.09	100.00	40.00	86.67	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.28	94.90	84.09	100.00	40.00	86.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.82	98.36	96.63	100.00	90.62	95.83	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	96.79	97.17	95.45		100.00	94.55
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_256	96.14	96.46	94.87		100.00	93.22
u_reg	99.52	99.83	97.74	100.00		100.00	100.00
u_tlul_adapter	97.46	98.54	100.00			98.44	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		157	149	94.90
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	135	15	9	60.00
ALWAYS	177	3	3	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	8	8	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
ALWAYS	243	6	6	100.00
ALWAYS	253	4	4	100.00
ALWAYS	268	6	6	100.00
ALWAYS	281	4	4	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
ALWAYS	403	3	3	100.00
ALWAYS	411	11	9	81.82
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
ALWAYS	584	6	6	100.00
CONT_ASSIGN	600	1	1	100.00
ALWAYS	605	6	6	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	656	1	1	100.00
ALWAYS	658	3	3	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	686	6	6	100.00
ALWAYS	693	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
122	1	1
123	1	1
135	1	1
136	1	1
138	1	1
140	1	1
142	1	1
143	1	1
145	0	1
			MISSING_ELSE
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
157	0	1
161	0	1
			==> MISSING_ELSE
166	0	1
167	0	1
168	0	1
			==> MISSING_ELSE
177	1	1
178	1	1
180	1	1
185	1	1
186	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
			MISSING_ELSE
206	8	8
208	8	8
209	8	8
214	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
232	1	1
233	1	1
238	1	1
239	1	1
240	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
			MISSING_ELSE
253	1	1
254	1	1
261	1	1
262	1	1
			MISSING_ELSE
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
			MISSING_ELSE
287	1	1
331	1	1
334	1	1
338	1	1
339	1	1
341	1	1
342	1	1
343	1	1
344	1	1
398	1	1
403	1	1
404	1	1
405	1	1
411	1	1
412	1	1
414	1	1
415	1	1
416	0	1
			MISSING_ELSE
418	1	1
419	0	1
			MISSING_ELSE
			MISSING_ELSE
422	1	1
423	1	1
424	1	1
425	1	1
			MISSING_ELSE
430	1	1
431	1	1
439	1	1
440	1	1
551	1	1
579	1	1
580	1	1
581	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
			MISSING_ELSE
592	1	1
600	1	1
605	1	1
606	1	1
608	1	1
612	1	1
616	1	1
620	1	1
633	1	1
652	1	1
656	1	1
658	1	1
659	1	1
661	1	1
664	1	1
686	2	2
687	2	2
688	2	2
			MISSING_ELSE
693	2	2
694	2	2
695	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	95	74	77.89
Logical	95	74	77.89
Non-Logical	0	0
Event	0	0

 LINE       157
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       226
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       227
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       228
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       229
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T4,T5
1	1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       240
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       287
 EXPRESSION (fifo_empty & ((~fifo_empty_q)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       334
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T2,T9,T10
1	1	1	Covered	T1,T2,T3

 LINE       343
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       343
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

 LINE       344
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       351
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T7,T4,T5
1	1	1	1	Covered	T1,T2,T3

 LINE       424
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T2,T9,T10
1	1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       551
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T14,T15

 LINE       579
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       579
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       580
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

 LINE       580
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       581
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

 LINE       600
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T4

 LINE       600
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T4,T5
0	0	1	0	Covered	T7,T4,T5
0	1	0	0	Covered	T3,T7,T4
1	0	0	0	Covered	T4,T5,T6

 LINE       652
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T11
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T16,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T17,T12	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T18	Yes	T2,T10,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T7,T19,T20	Yes	T7,T19,T20	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T12,T14,T15	Yes	T12,T14,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T12,T14,T15	Yes	T12,T14,T15	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T7,T4	Yes	T3,T7,T4	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	152	Covered	T1,T2,T3
DoneAwaitHashComplete	161	Not Covered
DoneAwaitHashDone	142	Covered	T1,T2,T3
DoneAwaitMessageComplete	145	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	142	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	145	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	168	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	152	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	161	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		60	52	86.67
TERNARY	343	2	2	100.00
TERNARY	344	2	2	100.00
CASE	138	10	4	40.00
IF	177	2	2	100.00
IF	189	4	4	100.00
IF	243	4	4	100.00
IF	253	3	3	100.00
IF	268	4	4	100.00
IF	281	3	3	100.00
IF	411	9	7	77.78
IF	585	2	2	100.00
CASE	606	5	5	100.00
IF	658	2	2	100.00
IF	686	4	4	100.00
IF	693	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	343	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	case (done_state_q)
-2-:	140	if (sha_hash_process)
-3-:	143	if (reg_hash_stop)
-4-:	150	if (reg_hash_done)
-5-:	157	if ((sha_message_length[8:0] == '0))
-6-:	166	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	177	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if ((!rst_ni))
-2-:	191	if (wipe_secret)
-3-:	193	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if ((!rst_ni))
-2-:	245	if (hash_start_or_continue)
-3-:	247	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))
-2-:	261	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if (hash_start_or_continue)
-3-:	272	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if ((!hmac_fifo_wsel))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T11

	LineNo.	Expression
-1-:	411	if ((!rst_ni))
-2-:	414	if ((!cfg_block))
-3-:	415	if (reg2hw.msg_length_lower.qe)
-4-:	418	if (reg2hw.msg_length_upper.qe)
-5-:	422	if (hash_start)
-6-:	424	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	606	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T4,T5,T6
update_seckey_inprocess	Covered	T3,T7,T4
hash_start_active	Covered	T7,T4,T5
msg_push_not_allowed	Covered	T7,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	658	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	if ((!rst_ni))
-2-:	687	if (reg_hash_process)
-3-:	688	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	693	if ((!rst_ni))
-2-:	694	if (hash_start_or_continue)
-3-:	695	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	367591876	367521080	0	0
FpvSecCmRegWeOnehotCheck_A	367591876	120	0	0
IntrFifoEmptyOKnown	367591876	367521080	0	0
IntrHmacDoneOKnown	367591876	367521080	0	0
TlOAReadyKnown	367591876	367521080	0	0
TlODValidKnown	367591876	367521080	0	0
ValidHashProcessAssert	367591876	40786	0	0
ValidHmacEnConditionAssert	367591876	10186	0	0
ValidWriteAssert	367591876	22839114	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	367591876	22839114	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	120	0	0
T23	8121	30	0	0
T24	0	30	0	0
T25	0	20	0	0
T26	0	10	0	0
T27	0	30	0	0
T28	335555	0	0	0
T29	73317	0	0	0
T30	5050	0	0	0
T31	32724	0	0	0
T32	306846	0	0	0
T33	1005	0	0	0
T34	102340	0	0	0
T35	413116	0	0	0
T36	1475	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	40786	0	0
T1	16424	7	0	0
T2	15443	6	0	0
T3	240080	194	0	0
T9	106473	36	0	0
T10	31187	10	0	0
T11	14163	39	0	0
T12	1037	0	0	0
T17	101861	25	0	0
T18	0	13	0	0
T21	9830	26	0	0
T22	239168	39	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	10186	0	0
T1	16424	5	0	0
T2	15443	3	0	0
T3	240080	0	0	0
T9	106473	18	0	0
T10	31187	4	0	0
T11	14163	20	0	0
T12	1037	0	0	0
T17	101861	11	0	0
T18	0	1	0	0
T21	9830	15	0	0
T22	239168	17	0	0
T37	0	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		157	149	94.90
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	135	15	9	60.00
ALWAYS	177	3	3	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	8	8	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
ALWAYS	243	6	6	100.00
ALWAYS	253	4	4	100.00
ALWAYS	268	6	6	100.00
ALWAYS	281	4	4	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
ALWAYS	403	3	3	100.00
ALWAYS	411	11	9	81.82
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
ALWAYS	584	6	6	100.00
CONT_ASSIGN	600	1	1	100.00
ALWAYS	605	6	6	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	656	1	1	100.00
ALWAYS	658	3	3	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	686	6	6	100.00
ALWAYS	693	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
122	1	1
123	1	1
135	1	1
136	1	1
138	1	1
140	1	1
142	1	1
143	1	1
145	0	1
			MISSING_ELSE
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
157	0	1
161	0	1
			==> MISSING_ELSE
166	0	1
167	0	1
168	0	1
			==> MISSING_ELSE
177	1	1
178	1	1
180	1	1
185	1	1
186	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
			MISSING_ELSE
206	8	8
208	8	8
209	8	8
214	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
232	1	1
233	1	1
238	1	1
239	1	1
240	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
			MISSING_ELSE
253	1	1
254	1	1
261	1	1
262	1	1
			MISSING_ELSE
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
			MISSING_ELSE
287	1	1
331	1	1
334	1	1
338	1	1
339	1	1
341	1	1
342	1	1
343	1	1
344	1	1
398	1	1
403	1	1
404	1	1
405	1	1
411	1	1
412	1	1
414	1	1
415	1	1
416	0	1
			MISSING_ELSE
418	1	1
419	0	1
			MISSING_ELSE
			MISSING_ELSE
422	1	1
423	1	1
424	1	1
425	1	1
			MISSING_ELSE
430	1	1
431	1	1
439	1	1
440	1	1
551	1	1
579	1	1
580	1	1
581	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
			MISSING_ELSE
592	1	1
600	1	1
605	1	1
606	1	1
608	1	1
612	1	1
616	1	1
620	1	1
633	1	1
652	1	1
656	1	1
658	1	1
659	1	1
661	1	1
664	1	1
686	2	2
687	2	2
688	2	2
			MISSING_ELSE
693	2	2
694	2	2
695	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	88	74	84.09
Logical	88	74	84.09
Non-Logical	0	0
Event	0	0

 LINE       157
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       226
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       227
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       228
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       229
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T4,T5
1	1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       240
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       287
 EXPRESSION (fifo_empty & ((~fifo_empty_q)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       334
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T2,T9,T10
1	1	1	Covered	T1,T2,T3

 LINE       343
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       343
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

 LINE       344
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       351
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T7,T4,T5
1	1	1	1	Covered	T1,T2,T3

 LINE       424
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Unreachable	T2,T9,T10
1	1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       551
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T14,T15

 LINE       579
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       579
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       580
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

 LINE       580
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       581
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

 LINE       600
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T4

 LINE       600
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T4,T5
0	0	1	0	Covered	T7,T4,T5
0	1	0	0	Covered	T3,T7,T4
1	0	0	0	Covered	T4,T5,T6

 LINE       652
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T11
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T16,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T17,T12	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T18	Yes	T2,T10,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T7,T19,T20	Yes	T7,T19,T20	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T12,T14,T15	Yes	T12,T14,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T12,T14,T15	Yes	T12,T14,T15	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T7,T4	Yes	T3,T7,T4	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	152	Covered	T1,T2,T3
DoneAwaitHashComplete	161	Not Covered
DoneAwaitHashDone	142	Covered	T1,T2,T3
DoneAwaitMessageComplete	145	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	142	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	145	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	168	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	152	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	161	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		60	52	86.67
TERNARY	343	2	2	100.00
TERNARY	344	2	2	100.00
CASE	138	10	4	40.00
IF	177	2	2	100.00
IF	189	4	4	100.00
IF	243	4	4	100.00
IF	253	3	3	100.00
IF	268	4	4	100.00
IF	281	3	3	100.00
IF	411	9	7	77.78
IF	585	2	2	100.00
CASE	606	5	5	100.00
IF	658	2	2	100.00
IF	686	4	4	100.00
IF	693	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	343	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	case (done_state_q)
-2-:	140	if (sha_hash_process)
-3-:	143	if (reg_hash_stop)
-4-:	150	if (reg_hash_done)
-5-:	157	if ((sha_message_length[8:0] == '0))
-6-:	166	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	177	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if ((!rst_ni))
-2-:	191	if (wipe_secret)
-3-:	193	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if ((!rst_ni))
-2-:	245	if (hash_start_or_continue)
-3-:	247	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))
-2-:	261	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if (hash_start_or_continue)
-3-:	272	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if ((!hmac_fifo_wsel))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T11

	LineNo.	Expression
-1-:	411	if ((!rst_ni))
-2-:	414	if ((!cfg_block))
-3-:	415	if (reg2hw.msg_length_lower.qe)
-4-:	418	if (reg2hw.msg_length_upper.qe)
-5-:	422	if (hash_start)
-6-:	424	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	606	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T4,T5,T6
update_seckey_inprocess	Covered	T3,T7,T4
hash_start_active	Covered	T7,T4,T5
msg_push_not_allowed	Covered	T7,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	658	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	if ((!rst_ni))
-2-:	687	if (reg_hash_process)
-3-:	688	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	693	if ((!rst_ni))
-2-:	694	if (hash_start_or_continue)
-3-:	695	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	367591876	367521080	0	0
FpvSecCmRegWeOnehotCheck_A	367591876	120	0	0
IntrFifoEmptyOKnown	367591876	367521080	0	0
IntrHmacDoneOKnown	367591876	367521080	0	0
TlOAReadyKnown	367591876	367521080	0	0
TlODValidKnown	367591876	367521080	0	0
ValidHashProcessAssert	367591876	40786	0	0
ValidHmacEnConditionAssert	367591876	10186	0	0
ValidWriteAssert	367591876	22839114	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	367591876	22839114	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	367591876	22839114	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	120	0	0
T23	8121	30	0	0
T24	0	30	0	0
T25	0	20	0	0
T26	0	10	0	0
T27	0	30	0	0
T28	335555	0	0	0
T29	73317	0	0	0
T30	5050	0	0	0
T31	32724	0	0	0
T32	306846	0	0	0
T33	1005	0	0	0
T34	102340	0	0	0
T35	413116	0	0	0
T36	1475	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	367521080	0	0
T1	16424	16369	0	0
T2	15443	15382	0	0
T3	240080	240074	0	0
T9	106473	106417	0	0
T10	31187	31107	0	0
T11	14163	14111	0	0
T12	1037	985	0	0
T17	101861	101774	0	0
T21	9830	9772	0	0
T22	239168	239101	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	40786	0	0
T1	16424	7	0	0
T2	15443	6	0	0
T3	240080	194	0	0
T9	106473	36	0	0
T10	31187	10	0	0
T11	14163	39	0	0
T12	1037	0	0	0
T17	101861	25	0	0
T18	0	13	0	0
T21	9830	26	0	0
T22	239168	39	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	10186	0	0
T1	16424	5	0	0
T2	15443	3	0	0
T3	240080	0	0	0
T9	106473	18	0	0
T10	31187	4	0	0
T11	14163	20	0	0
T12	1037	0	0	0
T17	101861	11	0	0
T18	0	1	0	0
T21	9830	15	0	0
T22	239168	17	0	0
T37	0	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	367591876	22839114	0	0
T1	16424	2796	0	0
T2	15443	8564	0	0
T3	240080	74193	0	0
T9	106473	74165	0	0
T10	31187	21639	0	0
T11	14163	480	0	0
T12	1037	0	0	0
T17	101861	8900	0	0
T18	0	11706	0	0
T21	9830	238	0	0
T22	239168	22761	0	0