Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256	83.33	100.00	66.67

---

Module Instance : tb.dut.u_prim_sha2_256

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.14	96.46	94.87		100.00	93.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sha256_logic.u_prim_sha2_256	96.30	96.39	95.61		100.00	93.22

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
ALWAYS	246	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
47	1	1
246	1	1
247	1	1
248	1	1

---

Cond Coverage for Module : prim_sha2_32

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3