Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38749422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36327806

1

T1

5

T2

1

T3

2695

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35861842	1			T1	1		T2	1		T3	2784
values[0x0]	18379964	1			T1	4		T3	1184		T4	2458
values[0x1]	20835422	1			T1	8		T3	1279		T4	2834

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29853696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45223532

1

T1

7

T2

1

T3

3318

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2094891	1			T4	35		T5	24		T7	76
valid_sources[0x01]	208539	1			T4	45		T5	24		T7	73
valid_sources[0x02]	210162	1			T4	33		T5	19		T7	64
valid_sources[0x03]	209907	1			T4	44		T5	25		T7	74
valid_sources[0x04]	211216	1			T4	43		T5	21		T7	102
valid_sources[0x05]	209551	1			T4	51		T5	42		T7	76
valid_sources[0x06]	210462	1			T4	58		T5	17		T7	68
valid_sources[0x07]	212820	1			T4	50		T5	11		T7	69
valid_sources[0x08]	216778	1			T4	38		T5	3		T7	87
valid_sources[0x09]	219486	1			T4	39		T5	23		T7	68
valid_sources[0x0a]	277870	1			T4	50		T5	9		T7	69
valid_sources[0x0b]	212694	1			T4	43		T5	13		T7	65
valid_sources[0x0c]	321406	1			T4	38		T7	70		T6	50
valid_sources[0x0d]	219994	1			T4	27		T5	7		T7	63
valid_sources[0x0e]	253524	1			T4	32		T5	11		T7	82
valid_sources[0x0f]	209808	1			T4	50		T5	20		T7	66
valid_sources[0x10]	286861	1			T4	46		T5	17		T27	1
valid_sources[0x11]	211783	1			T4	55		T5	11		T7	90
valid_sources[0x12]	221621	1			T4	46		T5	22		T7	74
valid_sources[0x13]	210297	1			T4	54		T5	11		T7	71
valid_sources[0x14]	210062	1			T4	45		T5	10		T7	85
valid_sources[0x15]	209358	1			T4	36		T5	17		T7	89
valid_sources[0x16]	209048	1			T4	52		T5	14		T7	68
valid_sources[0x17]	209829	1			T4	49		T5	5		T7	72
valid_sources[0x18]	344092	1			T4	44		T7	68		T6	28
valid_sources[0x19]	209280	1			T4	51		T5	25		T7	65
valid_sources[0x1a]	252068	1			T4	40		T5	16		T7	72
valid_sources[0x1b]	236999	1			T4	41		T5	15		T7	75
valid_sources[0x1c]	209742	1			T4	45		T5	26		T7	77
valid_sources[0x1d]	210806	1			T4	53		T5	26		T7	92
valid_sources[0x1e]	209081	1			T4	47		T5	12		T7	69
valid_sources[0x1f]	207787	1			T4	43		T5	8		T7	65
valid_sources[0x20]	208097	1			T4	30		T5	27		T7	79
valid_sources[0x21]	282060	1			T4	34		T5	32		T7	77
valid_sources[0x22]	590847	1			T4	49		T5	12		T7	65
valid_sources[0x23]	803081	1			T4	33		T5	22		T7	73
valid_sources[0x24]	523545	1			T4	41		T7	78		T6	37
valid_sources[0x25]	208654	1			T4	26		T5	20		T7	72
valid_sources[0x26]	291917	1			T4	39		T5	16		T7	67
valid_sources[0x27]	377198	1			T1	13		T4	38		T5	17
valid_sources[0x28]	211009	1			T4	52		T5	9		T7	77
valid_sources[0x29]	209926	1			T4	41		T5	20		T7	68
valid_sources[0x2a]	210998	1			T4	33		T5	13		T7	79
valid_sources[0x2b]	283631	1			T4	44		T5	35		T7	77
valid_sources[0x2c]	210292	1			T4	46		T5	7		T7	71
valid_sources[0x2d]	824907	1			T4	35		T5	13		T7	87
valid_sources[0x2e]	209118	1			T4	31		T5	12		T7	75
valid_sources[0x2f]	210398	1			T4	37		T5	13		T7	75
valid_sources[0x30]	210107	1			T4	37		T5	16		T7	82
valid_sources[0x31]	345972	1			T4	43		T5	8		T7	68
valid_sources[0x32]	211695	1			T4	51		T5	20		T7	75
valid_sources[0x33]	209037	1			T4	42		T5	17		T7	74
valid_sources[0x34]	208690	1			T4	46		T5	4		T7	83
valid_sources[0x35]	211104	1			T4	44		T5	6		T7	82
valid_sources[0x36]	209388	1			T4	38		T5	7		T7	72
valid_sources[0x37]	208266	1			T4	53		T5	13		T7	77
valid_sources[0x38]	212374	1			T4	37		T5	1		T7	79
valid_sources[0x39]	209743	1			T4	42		T5	13		T7	81
valid_sources[0x3a]	847851	1			T4	33		T7	75		T6	42
valid_sources[0x3b]	233543	1			T4	39		T5	5		T7	66
valid_sources[0x3c]	264341	1			T4	45		T5	26		T7	90
valid_sources[0x3d]	286380	1			T2	1		T4	40		T5	16
valid_sources[0x3e]	261471	1			T4	44		T5	2		T7	74
valid_sources[0x3f]	212567	1			T4	52		T5	23		T7	74
valid_sources[0x40]	207548	1			T4	50		T5	26		T7	62
valid_sources[0x41]	208358	1			T4	38		T5	17		T7	60
valid_sources[0x42]	208320	1			T4	35		T5	17		T7	78
valid_sources[0x43]	210555	1			T4	60		T5	4		T7	77
valid_sources[0x44]	208293	1			T4	43		T5	10		T7	71
valid_sources[0x45]	724049	1			T4	41		T5	8		T7	77
valid_sources[0x46]	208101	1			T4	44		T5	9		T7	80
valid_sources[0x47]	208993	1			T4	31		T5	13		T7	72
valid_sources[0x48]	295101	1			T4	51		T5	12		T7	82
valid_sources[0x49]	207998	1			T4	37		T5	8		T7	79
valid_sources[0x4a]	209382	1			T4	32		T5	14		T7	64
valid_sources[0x4b]	208836	1			T4	57		T5	21		T7	63
valid_sources[0x4c]	213819	1			T4	41		T5	36		T7	81
valid_sources[0x4d]	276857	1			T4	35		T5	2		T7	76
valid_sources[0x4e]	219458	1			T4	36		T5	4		T7	73
valid_sources[0x4f]	209507	1			T4	53		T5	12		T7	72
valid_sources[0x50]	315060	1			T4	54		T5	10		T7	96
valid_sources[0x51]	208282	1			T4	26		T5	23		T7	91
valid_sources[0x52]	234994	1			T4	49		T5	4		T7	73
valid_sources[0x53]	2125919	1			T4	35		T5	9		T7	79
valid_sources[0x54]	212573	1			T4	45		T5	42		T7	75
valid_sources[0x55]	210100	1			T4	41		T5	8		T7	76
valid_sources[0x56]	208784	1			T4	43		T5	3		T7	88
valid_sources[0x57]	269917	1			T4	43		T5	18		T7	92
valid_sources[0x58]	209092	1			T4	43		T5	33		T7	79
valid_sources[0x59]	1909378	1			T4	35		T5	4		T7	72
valid_sources[0x5a]	211515	1			T4	40		T5	13		T7	81
valid_sources[0x5b]	210209	1			T4	46		T5	30		T7	77
valid_sources[0x5c]	216822	1			T4	52		T5	19		T7	70
valid_sources[0x5d]	210204	1			T4	47		T5	5		T7	76
valid_sources[0x5e]	328965	1			T4	48		T5	40		T28	3
valid_sources[0x5f]	247332	1			T4	45		T5	6		T7	75
valid_sources[0x60]	211085	1			T4	41		T5	19		T7	91
valid_sources[0x61]	208909	1			T4	32		T5	24		T7	88
valid_sources[0x62]	210907	1			T4	46		T5	6		T7	64
valid_sources[0x63]	209565	1			T4	53		T5	28		T7	61
valid_sources[0x64]	210690	1			T4	47		T5	19		T7	73
valid_sources[0x65]	216176	1			T4	48		T5	11		T7	70
valid_sources[0x66]	209291	1			T4	41		T7	71		T6	45
valid_sources[0x67]	208785	1			T4	40		T5	26		T7	55
valid_sources[0x68]	208175	1			T4	55		T5	6		T7	65
valid_sources[0x69]	270428	1			T4	39		T5	39		T7	85
valid_sources[0x6a]	209195	1			T4	47		T5	17		T7	73
valid_sources[0x6b]	209944	1			T4	47		T5	16		T7	68
valid_sources[0x6c]	210268	1			T4	53		T5	13		T7	63
valid_sources[0x6d]	360755	1			T4	46		T5	3		T7	64
valid_sources[0x6e]	326112	1			T4	39		T5	6		T7	82
valid_sources[0x6f]	299993	1			T4	52		T5	21		T7	84
valid_sources[0x70]	222213	1			T4	33		T5	11		T7	79
valid_sources[0x71]	209293	1			T4	46		T5	13		T7	100
valid_sources[0x72]	211629	1			T4	54		T5	7		T7	81
valid_sources[0x73]	445742	1			T4	46		T5	23		T7	71
valid_sources[0x74]	217121	1			T4	40		T5	21		T7	79
valid_sources[0x75]	209825	1			T4	50		T7	98		T6	64
valid_sources[0x76]	216783	1			T4	40		T5	19		T7	93
valid_sources[0x77]	211235	1			T4	39		T5	12		T7	77
valid_sources[0x78]	261622	1			T4	56		T5	8		T7	86
valid_sources[0x79]	209741	1			T4	44		T5	16		T7	71
valid_sources[0x7a]	210055	1			T4	50		T5	3		T7	70
valid_sources[0x7b]	210213	1			T4	43		T5	7		T7	76
valid_sources[0x7c]	209308	1			T4	35		T5	20		T7	86
valid_sources[0x7d]	209793	1			T4	39		T5	13		T7	74
valid_sources[0x7e]	297995	1			T4	48		T5	7		T7	69
valid_sources[0x7f]	211319	1			T4	61		T5	17		T7	70
valid_sources[0x80]	279927	1			T4	37		T5	12		T7	89

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17712166

1

T1

1

T2

1

T3

1312

values[0x0]

all_enables

biggest_size

10037412

1

T1

2

T3

740

T4

1564

values[0x1]

all_enables

biggest_size

8578228

1

T1

2

T3

643

T4

1449