Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47292037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

44433289

1

T1

193

T2

1

T3

424

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43867499	1			T1	211		T2	1		T3	181
values[0x0]	22395682	1			T1	102		T2	1		T3	180
values[0x1]	25462145	1			T1	112		T3	203		T4	1248

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36390443	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

55334883

1

T1

250

T2

1

T3

458

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	281894	1			T3	1		T4	17		T6	46
valid_sources[0x01]	284720	1			T3	1		T4	16		T6	17
valid_sources[0x02]	282582	1			T3	1		T4	20		T6	40
valid_sources[0x03]	325161	1			T4	19		T6	40		T7	24
valid_sources[0x04]	323557	1			T3	1		T4	18		T6	39
valid_sources[0x05]	295159	1			T3	4		T4	23		T6	40
valid_sources[0x06]	285508	1			T3	3		T4	24		T6	40
valid_sources[0x07]	366002	1			T3	5		T4	21		T6	21
valid_sources[0x08]	348976	1			T3	1		T4	21		T6	21
valid_sources[0x09]	396907	1			T3	1		T4	18		T6	35
valid_sources[0x0a]	287879	1			T3	3		T4	13		T6	48
valid_sources[0x0b]	288447	1			T3	4		T4	13		T6	27
valid_sources[0x0c]	288983	1			T3	1		T4	17		T6	44
valid_sources[0x0d]	289933	1			T4	19		T6	34		T7	24
valid_sources[0x0e]	327917	1			T3	4		T4	25		T6	32
valid_sources[0x0f]	283217	1			T3	2		T4	16		T6	36
valid_sources[0x10]	292286	1			T3	2		T4	18		T6	29
valid_sources[0x11]	308850	1			T3	3		T4	14		T6	38
valid_sources[0x12]	419288	1			T3	3		T4	23		T6	33
valid_sources[0x13]	282086	1			T3	3		T4	13		T6	45
valid_sources[0x14]	283318	1			T3	1		T4	16		T6	47
valid_sources[0x15]	287838	1			T3	4		T4	19		T6	35
valid_sources[0x16]	319154	1			T4	17		T6	32		T7	45
valid_sources[0x17]	328363	1			T3	4		T4	14		T6	31
valid_sources[0x18]	399603	1			T3	2		T4	10		T6	35
valid_sources[0x19]	287962	1			T4	19		T6	31		T7	42
valid_sources[0x1a]	293507	1			T3	3		T4	20		T6	41
valid_sources[0x1b]	294063	1			T3	3		T4	32		T6	43
valid_sources[0x1c]	414528	1			T3	2		T4	20		T6	27
valid_sources[0x1d]	298351	1			T3	2		T4	23		T6	33
valid_sources[0x1e]	289592	1			T3	1		T4	26		T6	34
valid_sources[0x1f]	880903	1			T3	3		T4	19		T6	30
valid_sources[0x20]	290597	1			T3	1		T4	19		T6	34
valid_sources[0x21]	289650	1			T3	1		T4	15		T6	33
valid_sources[0x22]	443698	1			T3	2		T4	25		T6	38
valid_sources[0x23]	293243	1			T3	1		T4	23		T6	30
valid_sources[0x24]	286588	1			T3	4		T4	20		T6	28
valid_sources[0x25]	346839	1			T3	1		T4	26		T6	20
valid_sources[0x26]	331765	1			T3	3		T4	14		T6	35
valid_sources[0x27]	288082	1			T3	1		T4	16		T6	53
valid_sources[0x28]	287231	1			T3	3		T4	22		T6	27
valid_sources[0x29]	1976425	1			T3	2		T4	21		T6	39
valid_sources[0x2a]	345687	1			T3	6		T4	13		T6	27
valid_sources[0x2b]	284599	1			T3	1		T4	13		T6	37
valid_sources[0x2c]	287228	1			T3	1		T4	16		T6	43
valid_sources[0x2d]	370366	1			T3	2		T4	19		T6	45
valid_sources[0x2e]	987283	1			T4	18		T6	39		T7	40
valid_sources[0x2f]	289609	1			T4	20		T6	44		T7	17
valid_sources[0x30]	277626	1			T3	3		T4	20		T6	43
valid_sources[0x31]	284021	1			T3	5		T4	20		T6	43
valid_sources[0x32]	287481	1			T3	2		T4	18		T6	54
valid_sources[0x33]	285495	1			T3	2		T4	20		T6	43
valid_sources[0x34]	280520	1			T3	2		T4	16		T6	34
valid_sources[0x35]	283244	1			T3	1		T4	16		T6	44
valid_sources[0x36]	319981	1			T3	4		T4	14		T6	35
valid_sources[0x37]	308948	1			T3	1		T4	31		T6	31
valid_sources[0x38]	288971	1			T3	4		T4	20		T6	50
valid_sources[0x39]	295159	1			T4	17		T6	31		T7	48
valid_sources[0x3a]	281652	1			T3	1		T4	28		T6	24
valid_sources[0x3b]	287442	1			T3	2		T4	19		T6	31
valid_sources[0x3c]	317630	1			T3	3		T4	14		T6	44
valid_sources[0x3d]	283559	1			T3	6		T4	24		T6	39
valid_sources[0x3e]	298034	1			T3	2		T4	13		T6	38
valid_sources[0x3f]	284617	1			T3	3		T4	13		T6	42
valid_sources[0x40]	280062	1			T3	2		T4	20		T6	31
valid_sources[0x41]	282427	1			T3	7		T4	18		T6	34
valid_sources[0x42]	280173	1			T4	22		T6	34		T7	17
valid_sources[0x43]	299835	1			T3	3		T4	26		T6	38
valid_sources[0x44]	282964	1			T3	3		T4	16		T6	37
valid_sources[0x45]	322579	1			T3	2		T4	19		T6	22
valid_sources[0x46]	284226	1			T3	3		T4	28		T6	26
valid_sources[0x47]	797632	1			T3	1		T4	20		T6	34
valid_sources[0x48]	303713	1			T3	3		T4	13		T6	44
valid_sources[0x49]	309387	1			T3	1		T4	17		T19	2
valid_sources[0x4a]	288888	1			T4	15		T6	31		T7	23
valid_sources[0x4b]	279890	1			T4	22		T6	40		T7	44
valid_sources[0x4c]	396647	1			T3	1		T4	22		T6	26
valid_sources[0x4d]	284226	1			T3	3		T4	22		T6	38
valid_sources[0x4e]	279712	1			T3	2		T4	17		T6	14
valid_sources[0x4f]	346613	1			T3	3		T4	13		T6	34
valid_sources[0x50]	598679	1			T3	1		T4	17		T6	35
valid_sources[0x51]	354881	1			T3	1		T18	1		T4	17
valid_sources[0x52]	284528	1			T3	1		T4	18		T6	38
valid_sources[0x53]	441983	1			T3	5		T4	22		T6	32
valid_sources[0x54]	391327	1			T3	2		T4	12		T6	42
valid_sources[0x55]	291826	1			T3	2		T4	16		T6	37
valid_sources[0x56]	313196	1			T3	2		T4	23		T6	33
valid_sources[0x57]	282152	1			T3	4		T4	16		T6	32
valid_sources[0x58]	279186	1			T4	20		T6	20		T7	25
valid_sources[0x59]	280279	1			T3	4		T4	25		T6	37
valid_sources[0x5a]	298035	1			T3	4		T4	18		T6	27
valid_sources[0x5b]	282180	1			T3	3		T4	25		T6	47
valid_sources[0x5c]	297175	1			T3	3		T4	22		T6	30
valid_sources[0x5d]	304502	1			T3	4		T4	14		T6	58
valid_sources[0x5e]	283495	1			T3	3		T4	23		T6	33
valid_sources[0x5f]	293878	1			T3	2		T4	16		T6	48
valid_sources[0x60]	282444	1			T3	2		T4	12		T6	44
valid_sources[0x61]	2685396	1			T3	3		T4	20		T6	43
valid_sources[0x62]	408135	1			T3	2		T4	11		T6	37
valid_sources[0x63]	300688	1			T3	1		T4	24		T6	39
valid_sources[0x64]	299510	1			T3	1		T4	18		T6	36
valid_sources[0x65]	288120	1			T2	2		T3	6		T4	14
valid_sources[0x66]	287810	1			T3	1		T4	19		T6	31
valid_sources[0x67]	284842	1			T3	2		T4	22		T6	36
valid_sources[0x68]	322103	1			T3	3		T4	18		T6	31
valid_sources[0x69]	281360	1			T3	3		T4	17		T6	61
valid_sources[0x6a]	581395	1			T3	1		T4	23		T6	30
valid_sources[0x6b]	279555	1			T3	1		T4	14		T6	39
valid_sources[0x6c]	341958	1			T3	1		T4	15		T6	43
valid_sources[0x6d]	292872	1			T3	1		T4	23		T6	38
valid_sources[0x6e]	288293	1			T4	17		T6	37		T7	60
valid_sources[0x6f]	296062	1			T3	1		T4	21		T6	33
valid_sources[0x70]	288945	1			T3	2		T4	14		T6	32
valid_sources[0x71]	289948	1			T3	1		T4	24		T6	42
valid_sources[0x72]	281047	1			T3	3		T4	22		T6	33
valid_sources[0x73]	288592	1			T3	2		T4	18		T6	31
valid_sources[0x74]	413891	1			T3	3		T4	17		T6	44
valid_sources[0x75]	408634	1			T3	1		T4	17		T6	40
valid_sources[0x76]	297851	1			T3	1		T4	24		T6	35
valid_sources[0x77]	311972	1			T3	1		T4	21		T6	46
valid_sources[0x78]	325033	1			T3	8		T4	19		T6	33
valid_sources[0x79]	285981	1			T3	2		T4	28		T6	50
valid_sources[0x7a]	288872	1			T3	6		T4	18		T6	38
valid_sources[0x7b]	286990	1			T3	4		T4	28		T6	39
valid_sources[0x7c]	286431	1			T3	2		T4	24		T6	43
valid_sources[0x7d]	291634	1			T3	3		T4	24		T6	44
valid_sources[0x7e]	287741	1			T4	20		T6	33		T7	19
valid_sources[0x7f]	289969	1			T3	1		T4	13		T6	39
valid_sources[0x80]	293790	1			T3	1		T4	17		T6	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21671119

1

T1

102

T2

1

T3

70

values[0x0]

all_enables

biggest_size

12263172

1

T1

51

T3

165

T4

660

values[0x1]

all_enables

biggest_size

10498998

1

T1

40

T3

189

T4

614