Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50464086

1

T1

232

T2

1

T3

140

full_word

44638853

1

T1

193

T2

1

T3

424

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95102509	1			T1	425		T2	2		T3	564
auto[TlIntgErrCmd]	152	1			T79	13		T80	5		T81	2
auto[TlIntgErrData]	131	1			T79	11		T80	7		T81	1
auto[TlIntgErrBoth]	147	1			T79	6		T80	8		T81	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44934631

1

T1

211

T2

1

T3

181

auto[1]

50168308

1

T1

214

T2

1

T3

383

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23181973	1			T1	109		T3	111		T4	1322
auto[TlIntgErrNone]	partial	auto[1]	27281724	1			T1	123		T2	1		T3	29
auto[TlIntgErrNone]	full_word	auto[0]	21752450	1			T1	102		T2	1		T3	70
auto[TlIntgErrNone]	full_word	auto[1]	22886362	1			T1	91		T3	354		T4	1274
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T79	5		T80	3		T149	4
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T79	7		T80	1		T81	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T80	1		T149	2		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T79	1		T154	1		T155	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T79	6		T80	3		T149	6
auto[TlIntgErrData]	partial	auto[1]	48	1			T79	4		T80	3		T81	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T154	1		T151	1		T156	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T79	1		T80	1		T149	2
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T79	3		T80	4		T81	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T79	2		T80	3		T81	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T149	1		T154	1		T153	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T79	1		T80	1		T81	1