Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40539850

1

T1

8

T3

2552

T4

5268

full_word

36444642

1

T1

5

T2

1

T3

2695

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76984072	1			T1	13		T2	1		T3	5247
auto[TlIntgErrCmd]	133	1			T61	5		T62	4		T63	14
auto[TlIntgErrData]	141	1			T61	4		T62	8		T63	6
auto[TlIntgErrBoth]	146	1			T61	11		T62	8		T63	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36460974

1

T1

1

T2

1

T3

2784

auto[1]

40523518

1

T1

12

T3

2463

T4

5292

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18702961	1			T3	1472		T4	2989		T5	1257
auto[TlIntgErrNone]	partial	auto[1]	21836504	1			T1	8		T3	1080		T4	2279
auto[TlIntgErrNone]	full_word	auto[0]	17757825	1			T1	1		T2	1		T3	1312
auto[TlIntgErrNone]	full_word	auto[1]	18686782	1			T1	4		T3	1383		T4	3013
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T61	3		T62	1		T63	6
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T61	2		T62	3		T63	8
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T134	1		T137	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T139	1		T140	1		T141	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T61	2		T62	4		T63	4
auto[TlIntgErrData]	partial	auto[1]	65	1			T61	2		T62	3		T63	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T62	1		T142	1		T143	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T139	1		T140	2		T141	2
auto[TlIntgErrBoth]	partial	auto[0]	69	1			T61	10		T62	3		T63	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T61	1		T62	5		T63	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T135	1		T144	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T134	1		T137	1		T140	1