Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

20414694

1

T1

154

T3

89023

T4

45456

full_word

19730729

1

T1

153

T2

1

T3

73808

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	40145073	1			T1	307		T2	1		T3	162831
auto[TlIntgErrCmd]	123	1			T50	2		T51	3		T52	4
auto[TlIntgErrData]	109	1			T50	6		T51	4		T52	2
auto[TlIntgErrBoth]	118	1			T50	2		T51	3		T52	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15527489

1

T1

133

T2

1

T3

65836

auto[1]

24617934

1

T1

174

T3

96995

T4

49737

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8151183	1			T1	72		T3	33222		T4	16833
auto[TlIntgErrNone]	partial	auto[1]	12263194	1			T1	82		T3	55801		T4	28623
auto[TlIntgErrNone]	full_word	auto[0]	7376136	1			T1	61		T2	1		T3	32614
auto[TlIntgErrNone]	full_word	auto[1]	12354560	1			T1	92		T3	41194		T4	21114
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T51	1		T52	1		T127	4
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T50	2		T51	2		T52	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T129	1		T133	2		T54	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T52	2		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T50	3		T51	2		T52	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T50	2		T51	2		T129	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T128	1		T134	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T50	1		T127	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T50	1		T51	1		T127	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T50	1		T51	2		T52	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T135	2		T132	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T52	1		T130	1		T135	2