Unified Coverage Report :: Module :: prim_sha2_pad

Module : prim_sha2_pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.22	95.00	90.77		60.00	83.10

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad	82.22	95.00	90.77		60.00	83.10

---

Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.22	95.00	90.77		60.00	83.10

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.22	95.00	90.77		60.00	83.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.81	98.64	94.29		90.00	92.31		gen_multimode_logic.u_prim_sha2_multimode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
TOTAL		120	114	95.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
ALWAYS	68	3	3	100.00
ALWAYS	83	23	22	95.65
ALWAYS	172	3	3	100.00
ALWAYS	178	69	65	94.20
ALWAYS	322	10	9	90.00
ALWAYS	340	3	3	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	349	3	3	100.00
CONT_ASSIGN	354	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
53	1	1
57	1	1
63	1	1
68	2	2
69	1	1
83	1	1
85	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
102	1	1
103	1	1
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
110	1	1
111	1	1
115	0	1
119	1	1
123	1	1
130	1	1
141	1	1(1 unreachable)
			MISSING_ELSE
172	2	2
173	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
192	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
215	1	1
217	1	1
218	1	1
219	1	1
220	1	1
225	1	1
226	1	1
227	1	1
233	1	1
234	1	1
235	1	1
239	1	1
240	1	1
241	1	1
243	1	1
244	1	1
273	1	1
274	1	1
276	1	1
277	1	1
278	2	2
279	1	1
281	1	1
286	1	1
287	1	1
289	1	1
290	1	1
291	1	1
293	0	1
294	0	1
299	1	1
300	1	1
302	1	1
303	1	1
304	1	1
306	0	1
307	0	1
316	2	2
317	2	2
			MISSING_ELSE
322	1	1
324	1	1
326	1	1
327	1	1
329	0	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
			==> MISSING_ELSE
			MISSING_ELSE
340	2	2
341	1	1
344	1	1
349	2	2
350	1	1
354	1	1

---

Cond Coverage for Module : prim_sha2_pad

	Total	Covered	Percent
Conditions	130	118	90.77
Logical	130	118	90.77
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       57
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T3,T4

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       57
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       57
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       57
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       63
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       94
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
             ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       94
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       123
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       123
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       123
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       123
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       123
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       130
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       130
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       188
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       198
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T3,T4

 LINE       209
 EXPRESSION (((tx_count == message_length_i) & MultimodeEn) || (((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
             -----------------------1----------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Unreachable
1	0	Covered	T1,T3,T4

 LINE       209
 SUB-EXPRESSION ((tx_count == message_length_i) & MultimodeEn)
                 ---------------1--------------   -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T6
1	-	Covered	T1,T3,T4

 LINE       209
 SUB-EXPRESSION (tx_count == message_length_i)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T3,T4

 LINE       227
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       227
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       233
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T7,T9

 LINE       239
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       331
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
             ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       331
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       333
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       344
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       344
 SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       354
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       354
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	9	60.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	190	Covered	T1,T3,T4
StIdle	182	Covered	T1,T2,T3
StLenHi	234	Covered	T1,T3,T4
StLenLo	290	Covered	T1,T3,T4
StPad00	240	Covered	T1,T3,T4
StPad80	203	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StFifoReceive->StIdle	182	Covered	T10,T11,T12
StFifoReceive->StPad80	203	Covered	T1,T3,T4
StIdle->StFifoReceive	190	Covered	T1,T3,T4
StLenHi->StFifoReceive	317	Not Covered
StLenHi->StIdle	182	Covered	T13,T11
StLenHi->StLenLo	290	Covered	T1,T3,T4
StLenLo->StFifoReceive	317	Not Covered
StLenLo->StIdle	182	Covered	T1,T3,T4
StPad00->StFifoReceive	317	Not Covered
StPad00->StIdle	182	Not Covered
StPad00->StLenHi	278	Covered	T1,T3,T4
StPad80->StFifoReceive	317	Not Covered
StPad80->StIdle	182	Not Covered
StPad80->StLenHi	234	Covered	T6,T7,T9
StPad80->StPad00	240	Covered	T1,T3,T4

---

Branch Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
Branches		71	59	83.10
TERNARY	57	3	3	100.00
TERNARY	63	3	3	100.00
TERNARY	344	3	3	100.00
IF	68	2	2	100.00
CASE	83	24	18	75.00
IF	141	1	1	100.00
IF	172	2	2	100.00
CASE	184	20	16	80.00
IF	316	3	3	100.00
IF	324	6	4	66.67
IF	340	2	2	100.00
IF	349	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	57	(((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? 
-2-:	57	(((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	((((~sha_en_i) || hash_go) || hash_done_i)) ? 
-2-:	63	(hash_process_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	344	(hash_start_i) ? 
-2-:	344	(hash_done_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	83	case (sel_data)
-2-:	94	if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)))
-3-:	95	case (message_length_i[4:3])
-4-:	102	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-5-:	103	case (message_length_i[5:3])
-6-:	123	(((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? 
-7-:	123	(((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? 
-8-:	130	(((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? 
-9-:	130	(((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
FifoIn	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Pad80	1	2'b00	-	-	-	-	-	-	Covered	T1,T3,T4
Pad80	1	2'b01	-	-	-	-	-	-	Covered	T3,T4,T5
Pad80	1	2'b10	-	-	-	-	-	-	Covered	T1,T6,T7
Pad80	1	2'b11	-	-	-	-	-	-	Covered	T5,T6,T7
Pad80	1	default	-	-	-	-	-	-	Not Covered
Pad80	0	-	1	3'b000	-	-	-	-	Covered	T3,T4,T5
Pad80	0	-	1	3'b001	-	-	-	-	Covered	T3,T4,T5
Pad80	0	-	1	3'b010	-	-	-	-	Covered	T7,T14,T15
Pad80	0	-	1	3'b011	-	-	-	-	Covered	T5,T7,T14
Pad80	0	-	1	3'b100	-	-	-	-	Covered	T7,T14,T15
Pad80	0	-	1	3'b101	-	-	-	-	Covered	T7,T14,T16
Pad80	0	-	1	3'b110	-	-	-	-	Covered	T7,T15,T17
Pad80	0	-	1	3'b111	-	-	-	-	Covered	T14,T15,T17
Pad80	0	-	1	default	-	-	-	-	Not Covered
Pad80	0	-	0	-	-	-	-	-	Not Covered
Pad00	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
LenHi	-	-	-	-	1	-	-	-	Covered	T1,T3,T4
LenHi	-	-	-	-	0	1	-	-	Covered	T3,T4,T5
LenHi	-	-	-	-	0	0	-	-	Not Covered
LenLo	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
LenLo	-	-	-	-	-	-	0	1	Covered	T3,T4,T5
LenLo	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	141	if ((!MultimodeEn))

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	172	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	case (st_q)
-2-:	188	if ((sha_en_i && hash_go))
-3-:	198	if ((fifo_partial && fifo_rvalid_i))
-4-:	204	if ((!hash_process_flag_q))
-5-:	209	if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
-6-:	227	(((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? 
-7-:	227	(((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? 
-8-:	233	if ((shaf_rready_i && txcnt_eq_1a0))
-9-:	239	if ((shaf_rready_i && (!txcnt_eq_1a0)))
-10-:	276	if (shaf_rready_i)
-11-:	278	if (txcnt_eq_1a0)
-12-:	289	if (shaf_rready_i)
-13-:	302	if (shaf_rready_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StFifoReceive	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StFifoReceive	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StFifoReceive	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
StPad80	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPad80	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T3,T4,T5
StPad80	-	-	-	-	0	0	-	-	-	-	-	-	Not Covered
StPad80	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T7,T9
StPad80	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T3,T4
StPad80	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T3,T4,T5
StPad00	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StPad00	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T3,T4
StPad00	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T6,T7,T9
StLenHi	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
StLenHi	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StLenLo	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	316	if ((!sha_en_i))
-2-:	317	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	324	if (hash_start_i)
-2-:	327	if (hash_continue_i)
-3-:	330	if (inc_txcount)
-4-:	331	if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn)))
-5-:	333	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T3,T4
0	1	-	-	-	Not Covered
0	0	1	1	-	Covered	T1,T3,T4
0	0	1	0	1	Covered	T3,T4,T5
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	340	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3