Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.81	98.64	94.29		90.00	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode	93.81	98.64	94.29		90.00	92.31

---

Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.81	98.64	94.29		90.00	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.38	97.00	92.59		72.00	87.92

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	94.37			97.62		u_prim_sha2_512

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	82.22	95.00	90.77		60.00	83.10

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		147	145	98.64
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	88	14	14	100.00
ALWAYS	113	4	4	100.00
ALWAYS	119	10	10	100.00
ALWAYS	136	3	3	100.00
ALWAYS	142	27	27	100.00
ALWAYS	181	3	3	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	278	7	7	100.00
ALWAYS	295	3	3	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	305	3	3	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	313	3	3	100.00
ALWAYS	326	3	3	100.00
ALWAYS	331	26	26	100.00
ALWAYS	382	3	3	100.00
ALWAYS	396	3	3	100.00
ALWAYS	403	3	3	100.00
CONT_ASSIGN	407	1	1	100.00
ALWAYS	410	23	21	91.30
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	486	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1
76	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
96	1	1
97	1	1
98	1	1
100	1	1
102	1	1
103	1	1
			==> MISSING_ELSE
105	1	1
107	1	1
			MISSING_ELSE
113	2	2
114	2	2
			==> MISSING_ELSE
119	1	1
120	1	1
121	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
			==> MISSING_ELSE
			MISSING_ELSE
136	2	2
137	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			==> MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
161	1	1
162	1	1
163	1	1
164	2	2
			MISSING_ELSE
166	1	1
168	1	1
169	1	1
170	1	1
172	1	1
173	1	1
			MISSING_ELSE
			MISSING_ELSE
181	2	2
182	1	1
186	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
286	1	1
288	1	1
			MISSING_ELSE
295	2	2
296	1	1
300	1	1
305	2	2
306	1	1
310	1	1
313	2	2
314	1	1
326	2	2
327	1	1
331	1	1
332	1	1
333	1	1
335	1	1
337	2	2
338	1	1
342	1	1
344	1	1
345	1	1
346	1	1
347	1	1
349	1	1
351	1	1
352	1	1
357	1	1
358	1	1
360	1	1
361	1	1
362	1	1
364	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
382	2	2
383	1	1
396	2	2
397	1	1
403	2	2
404	1	1
407	1	1
410	1	1
411	1	1
412	1	1
413	1	1
414	1	1
416	1	1
418	1	1
419	1	1
420	1	1
422	1	1
427	1	1
428	1	1
431	1	1
432	1	1
433	1	1
435	1	1
440	1	1
441	1	1
442	0	1
443	0	1
445	1	1
454	2	2
			MISSING_ELSE
457	1	1
483	1	1
486	1	1

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	140	132	94.29
Logical	140	132	94.29
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       76
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       76
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       91
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       98
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       125
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       128
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       128
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       128
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       147
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       149
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T5

 LINE       159
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       164
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       166
 EXPRESSION ((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_384))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       166
 SUB-EXPRESSION (hash_done_o == 1'b1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       166
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T5

 LINE       170
 EXPRESSION ((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_256))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       170
 SUB-EXPRESSION (hash_done_o == 1'b1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       170
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       279
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       300
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       300
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       300
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       346
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       357
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       407
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T10,T42
1	0	Covered	T1,T3,T4

 LINE       407
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T10,T42

 LINE       418
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       428
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4

 LINE       428
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       428
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T3,T4

 LINE       428
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       428
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       428
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       428
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T5

 LINE       428
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T5

 LINE       441
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       454
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       457
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       457
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       457
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T3,T4

 LINE       457
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       457
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       457
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       457
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       457
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       457
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       457
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       457
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       483
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       486
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	331	Covered	T1,T2,T3
FifoLoadFromFifo	337	Covered	T1,T3,T4
FifoWait	347	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	337	Covered	T1,T3,T4
FifoLoadFromFifo->FifoIdle	331	Covered	T10,T13,T11
FifoLoadFromFifo->FifoWait	347	Covered	T1,T3,T4
FifoWait->FifoIdle	331	Covered	T1,T3,T4
FifoWait->FifoLoadFromFifo	362	Covered	T1,T3,T4

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	420	Covered	T1,T3,T4
ShaIdle	422	Covered	T1,T2,T3
ShaUpdateDigest	433	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	454	Covered	T13,T11,T12
ShaCompress->ShaUpdateDigest	433	Covered	T1,T3,T4
ShaIdle->ShaCompress	420	Covered	T1,T3,T4
ShaUpdateDigest->ShaCompress	443	Not Covered
ShaUpdateDigest->ShaIdle	445	Covered	T1,T3,T4

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		78	72	92.31
TERNARY	76	3	3	100.00
TERNARY	300	3	3	100.00
TERNARY	457	3	3	100.00
IF	279	4	4	100.00
IF	295	2	2	100.00
IF	305	2	2	100.00
IF	313	2	2	100.00
IF	326	2	2	100.00
CASE	335	9	8	88.89
IF	373	3	3	100.00
IF	382	2	2	100.00
IF	396	2	2	100.00
IF	403	2	2	100.00
CASE	416	8	6	75.00
IF	454	2	2	100.00
IF	89	8	7	87.50
IF	113	3	2	66.67
IF	120	6	5	83.33
IF	136	2	2	100.00
IF	143	8	8	100.00
IF	181	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(hash_go) ? 
-2-:	76	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	(((~sha_en_i) || hash_go)) ? 
-2-:	300	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	457	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	457	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if (((!sha_en_i) || hash_go))
-2-:	281	if (run_hash)
-3-:	282	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T3,T4
0	1	0	Covered	T1,T3,T4
0	0	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	295	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	313	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	case (fifo_st_q)
-2-:	337	if (hash_go)
-3-:	342	if ((!shaf_rvalid))
-4-:	346	if ((w_index_q == 4'd15))
-5-:	357	if ((msg_feed_complete && one_chunk_done))
-6-:	361	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T1,T3,T4
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T3,T4
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T3,T4
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T3,T4
FifoWait	-	-	-	1	-	Covered	T1,T3,T4
FifoWait	-	-	-	0	1	Covered	T1,T3,T4
FifoWait	-	-	-	0	0	Covered	T1,T3,T4
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	373	if ((!sha_en_i))
-2-:	376	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	382	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	416	case (sha_st_q)
-2-:	418	if ((fifo_st_q == FifoWait))
-3-:	428	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	432	if (one_chunk_done)
-5-:	441	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T3,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T3,T4
ShaCompress	-	0	1	-	Covered	T1,T3,T4
ShaCompress	-	0	0	-	Covered	T1,T3,T4
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	454	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if (wipe_secret_i)
-2-:	91	if (((!sha_en_i) || hash_go))
-3-:	93	if (((!run_hash) && update_w_from_fifo))
-4-:	97	if (calculate_next_w)
-5-:	98	if ((digest_mode_flag_q == SHA2_256))
-6-:	102	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-7-:	105	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T35,T36,T37
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T3,T4
0	0	0	1	1	-	-	Covered	T1,T3,T4
0	0	0	1	0	1	-	Covered	T3,T4,T5
0	0	0	1	0	0	-	Not Covered
0	0	0	0	-	-	1	Covered	T1,T3,T4
0	0	0	0	-	-	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	114	if (MultimodeEn)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	120	if (wipe_secret_i)
-2-:	122	if (init_hash)
-3-:	124	if (run_hash)
-4-:	125	if ((digest_mode_flag_q == SHA2_256))
-5-:	128	if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T35,T36,T37
0	1	-	-	-	Covered	T1,T3,T4
0	0	1	1	-	Covered	T1,T3,T4
0	0	1	0	1	Covered	T3,T4,T5
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (wipe_secret_i)
-2-:	145	if (hash_start_i)
-3-:	155	if (clear_digest)
-4-:	157	if ((!sha_en_i))
-5-:	161	if (update_digest)
-6-:	166	if (((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_384)))
-7-:	170	if (((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_256)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T35,T36,T37
0	1	-	-	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	-	-	Covered	T27,T10,T42
0	0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	0	1	1	-	Covered	T3,T4,T5
0	0	0	0	1	0	1	Covered	T1,T3,T4
0	0	0	0	1	0	0	Covered	T1,T3,T4
0	0	0	0	0	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	181	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3