Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21864466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8812095

1

T26

227

T27

1135

T28

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25475211	1			T26	100		T27	960		T28	11
values[0x0]	2606015	1			T26	69		T27	478		T28	4
values[0x1]	2595335	1			T26	59		T27	481		T28	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16139310	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14537251

1

T26

227

T27

1272

T28

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	119710	1			T27	1		T52	1		T69	1
valid_sources[0x01]	122652	1			T27	26		T52	26		T2	27
valid_sources[0x02]	115870	1			T27	17		T52	17		T2	26
valid_sources[0x03]	116022	1			T27	14		T52	14		T2	10
valid_sources[0x04]	113825	1			T27	1		T52	1		T32	1
valid_sources[0x05]	121990	1			T27	4		T52	4		T30	11
valid_sources[0x06]	136863	1			T26	3		T28	7		T34	3
valid_sources[0x07]	115455	1			T27	3		T36	7		T52	3
valid_sources[0x08]	122942	1			T27	2		T28	1		T33	1
valid_sources[0x09]	121710	1			T27	5		T52	5		T2	10
valid_sources[0x0a]	120070	1			T27	12		T52	12		T2	9
valid_sources[0x0b]	120925	1			T27	5		T52	5		T2	41
valid_sources[0x0c]	111473	1			T27	5		T52	5		T30	2
valid_sources[0x0d]	120969	1			T27	3		T52	3		T30	2
valid_sources[0x0e]	131570	1			T26	7		T27	14		T34	7
valid_sources[0x0f]	112340	1			T27	8		T52	8		T2	32
valid_sources[0x10]	124102	1			T27	1		T52	1		T30	5
valid_sources[0x11]	108225	1			T26	4		T27	25		T34	4
valid_sources[0x12]	131415	1			T27	13		T52	13		T2	21
valid_sources[0x13]	107295	1			T26	21		T27	13		T34	21
valid_sources[0x14]	122170	1			T32	6		T74	6		T76	6
valid_sources[0x15]	122025	1			T27	3		T52	3		T30	13
valid_sources[0x16]	127776	1			T27	18		T29	4		T52	18
valid_sources[0x17]	117460	1			T27	6		T52	6		T30	19
valid_sources[0x18]	117210	1			T27	4		T52	4		T32	2
valid_sources[0x19]	116762	1			T26	5		T27	10		T34	5
valid_sources[0x1a]	127765	1			T30	6		T32	4		T31	6
valid_sources[0x1b]	122180	1			T27	16		T52	16		T2	33
valid_sources[0x1c]	119900	1			T2	45		T3	52		T4	72
valid_sources[0x1d]	118085	1			T26	4		T27	1		T34	4
valid_sources[0x1e]	120640	1			T27	2		T52	2		T30	2
valid_sources[0x1f]	116625	1			T27	13		T52	13		T2	27
valid_sources[0x20]	126370	1			T27	10		T52	10		T30	1
valid_sources[0x21]	114330	1			T27	4		T52	4		T2	13
valid_sources[0x22]	112717	1			T27	3		T52	3		T2	32
valid_sources[0x23]	106055	1			T26	2		T27	13		T34	2
valid_sources[0x24]	122280	1			T27	12		T52	12		T32	1
valid_sources[0x25]	125635	1			T26	1		T27	3		T34	1
valid_sources[0x26]	118955	1			T27	9		T52	9		T30	1
valid_sources[0x27]	119870	1			T27	8		T52	8		T30	3
valid_sources[0x28]	127765	1			T27	7		T29	9		T52	7
valid_sources[0x29]	117865	1			T26	3		T34	3		T53	3
valid_sources[0x2a]	125935	1			T27	9		T52	9		T30	6
valid_sources[0x2b]	118830	1			T27	2		T29	6		T52	2
valid_sources[0x2c]	141440	1			T27	8		T52	8		T30	4
valid_sources[0x2d]	118916	1			T27	22		T52	22		T2	19
valid_sources[0x2e]	120065	1			T27	1		T52	1		T30	1
valid_sources[0x2f]	128274	1			T26	4		T27	6		T34	4
valid_sources[0x30]	115200	1			T27	12		T52	12		T30	1
valid_sources[0x31]	113330	1			T27	4		T52	4		T32	8
valid_sources[0x32]	123975	1			T27	2		T52	2		T32	3
valid_sources[0x33]	117680	1			T27	6		T52	6		T2	19
valid_sources[0x34]	109523	1			T36	5		T30	10		T31	10
valid_sources[0x35]	117915	1			T27	2		T52	2		T32	3
valid_sources[0x36]	118645	1			T30	7		T31	7		T75	7
valid_sources[0x37]	119100	1			T27	2		T52	2		T32	2
valid_sources[0x38]	116245	1			T27	3		T52	3		T30	1
valid_sources[0x39]	119060	1			T27	1		T52	1		T69	1
valid_sources[0x3a]	120959	1			T27	13		T52	13		T30	12
valid_sources[0x3b]	126889	1			T26	2		T27	9		T34	2
valid_sources[0x3c]	118342	1			T27	8		T52	8		T30	2
valid_sources[0x3d]	117200	1			T2	29		T3	81		T4	94
valid_sources[0x3e]	127170	1			T27	4		T52	4		T2	11
valid_sources[0x3f]	108121	1			T27	1		T52	1		T2	20
valid_sources[0x40]	122115	1			T30	3		T31	3		T75	3
valid_sources[0x41]	119740	1			T27	4		T52	4		T30	5
valid_sources[0x42]	131835	1			T27	29		T52	29		T2	33
valid_sources[0x43]	120635	1			T27	7		T52	7		T2	19
valid_sources[0x44]	122325	1			T26	9		T27	13		T34	9
valid_sources[0x45]	131190	1			T32	2		T74	2		T76	2
valid_sources[0x46]	115930	1			T30	3		T32	1		T31	3
valid_sources[0x47]	122180	1			T27	9		T52	9		T30	2
valid_sources[0x48]	131040	1			T27	2		T52	2		T30	3
valid_sources[0x49]	113469	1			T27	9		T52	9		T30	1
valid_sources[0x4a]	133570	1			T27	4		T29	2		T52	4
valid_sources[0x4b]	117055	1			T26	8		T27	4		T34	8
valid_sources[0x4c]	125390	1			T36	2		T37	2		T38	2
valid_sources[0x4d]	119805	1			T27	21		T52	21		T2	22
valid_sources[0x4e]	123230	1			T26	2		T27	6		T34	2
valid_sources[0x4f]	127345	1			T27	1		T52	1		T32	2
valid_sources[0x50]	121735	1			T27	4		T52	4		T30	3
valid_sources[0x51]	115289	1			T26	2		T27	17		T34	2
valid_sources[0x52]	124110	1			T26	7		T34	7		T53	7
valid_sources[0x53]	112061	1			T27	3		T52	3		T30	3
valid_sources[0x54]	116025	1			T27	11		T52	11		T30	1
valid_sources[0x55]	114081	1			T26	7		T34	7		T36	1
valid_sources[0x56]	114785	1			T30	5		T32	1		T31	5
valid_sources[0x57]	115840	1			T27	22		T52	22		T30	4
valid_sources[0x58]	111725	1			T27	9		T52	9		T30	8
valid_sources[0x59]	136660	1			T26	13		T27	30		T34	13
valid_sources[0x5a]	115100	1			T2	24		T3	54		T4	105
valid_sources[0x5b]	116115	1			T26	2		T27	3		T34	2
valid_sources[0x5c]	117885	1			T26	1		T27	5		T34	1
valid_sources[0x5d]	112835	1			T27	1		T52	1		T30	5
valid_sources[0x5e]	122835	1			T26	4		T27	13		T34	4
valid_sources[0x5f]	120028	1			T32	1		T74	1		T76	1
valid_sources[0x60]	125565	1			T27	13		T52	13		T30	13
valid_sources[0x61]	112249	1			T26	1		T27	5		T34	1
valid_sources[0x62]	127710	1			T26	4		T27	6		T34	4
valid_sources[0x63]	116912	1			T26	2		T27	10		T34	2
valid_sources[0x64]	117630	1			T27	26		T52	26		T30	1
valid_sources[0x65]	114680	1			T27	11		T28	3		T33	3
valid_sources[0x66]	111590	1			T27	19		T52	19		T30	2
valid_sources[0x67]	122320	1			T2	23		T3	95		T4	113
valid_sources[0x68]	125460	1			T27	4		T52	4		T32	2
valid_sources[0x69]	115963	1			T27	11		T52	11		T2	46
valid_sources[0x6a]	122037	1			T27	24		T52	24		T30	5
valid_sources[0x6b]	125530	1			T30	1		T31	1		T75	1
valid_sources[0x6c]	117765	1			T27	18		T52	18		T69	5
valid_sources[0x6d]	124255	1			T27	7		T52	7		T30	1
valid_sources[0x6e]	125125	1			T27	1		T52	1		T32	1
valid_sources[0x6f]	118480	1			T27	3		T52	3		T30	3
valid_sources[0x70]	122770	1			T26	6		T27	8		T34	6
valid_sources[0x71]	126591	1			T27	17		T52	17		T30	2
valid_sources[0x72]	107065	1			T27	12		T52	12		T32	1
valid_sources[0x73]	118680	1			T26	1		T27	1		T34	1
valid_sources[0x74]	121090	1			T27	8		T52	8		T2	26
valid_sources[0x75]	118665	1			T27	31		T29	8		T52	31
valid_sources[0x76]	118940	1			T27	10		T52	10		T30	1
valid_sources[0x77]	116530	1			T26	5		T27	2		T34	5
valid_sources[0x78]	113180	1			T26	9		T34	9		T53	9
valid_sources[0x79]	127105	1			T27	21		T52	21		T2	29
valid_sources[0x7a]	108114	1			T27	6		T52	6		T30	1
valid_sources[0x7b]	109551	1			T27	14		T52	14		T32	2
valid_sources[0x7c]	113950	1			T27	10		T52	10		T2	19
valid_sources[0x7d]	122355	1			T27	3		T52	3		T30	2
valid_sources[0x7e]	121481	1			T26	1		T27	9		T34	1
valid_sources[0x7f]	131225	1			T27	3		T52	3		T2	53
valid_sources[0x80]	117140	1			T27	14		T52	14		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6842209

1

T26

99

T27

483

T28

5

values[0x0]

all_enables

biggest_size

1267043

1

T26

69

T27

350

T28

4

values[0x1]

all_enables

biggest_size

702843

1

T26

59

T27

302

T28

1