Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_level_cg

Group : i2c_env_pkg::i2c_fifo_level_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
82.35	73.53	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.rx_fifo_level_cg	64.71	1	100	1	64	64
i2c_env_pkg.fmt_fifo_level_cg	82.35	1	100	1	64	64

---

Group Instance : i2c_env_pkg.rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
64.71	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	1	8	88.89
Crosses	8	5	3	37.50

Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	1	4	80.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	5	3	37.50	100	1	1	0

---

Group Instance : i2c_env_pkg.fmt_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
82.35	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	3	5	62.50

Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	3	5	62.50	100	1	1	0

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_fifolvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
lvl[4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	31950	1			T2	3		T3	26		T4	77
lvl[1]	250	1			T54	2		T55	2		T101	3
lvl[8]	150	1			T54	2		T55	2		T101	1
lvl[16]	550	1			T54	5		T55	5		T101	6

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29950

1

T2

3

T3

26

T4

77

auto[1]

2950

1

T14

3

T54

6

T55

6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30400

1

T2

2

T3

25

T4

76

auto[1]

2500

1

T2

1

T3

1

T4

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	5	3	37.50	5
Automatically Generated Cross Bins	8	5	3	37.50	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Element holes

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[4]]	*	--	--	2

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[1]]	[auto[1]]	0	1	1
[lvl[8] , lvl[16]]	[auto[1]]	--	--	2

Covered bins

cp_fifolvl

cp_irq

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lvl[1]

auto[0]

250

1

T54

2

T55

2

T101

3

lvl[8]

auto[0]

150

1

T54

2

T55

2

T101

1

lvl[16]

auto[0]

550

1

T54

5

T55

5

T101

6

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	30550	1			T2	3		T3	26		T4	77
lvl[1]	1350	1			T9	2		T54	12		T55	12
lvl[4]	100	1			T54	1		T55	1		T101	1
lvl[8]	350	1			T54	3		T55	3		T101	4
lvl[16]	550	1			T54	5		T55	5		T101	6

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29100

1

T2

3

T3

26

T4

77

auto[1]

3800

1

T5

10

T9

11

T14

2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30150

1

T2

2

T3

25

T4

76

auto[1]

2750

1

T2

1

T3

1

T4

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	3	5	62.50	3
Automatically Generated Cross Bins	8	3	5	62.50	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[4] , lvl[8] , lvl[16]]	[auto[1]]	--	--	3

Covered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	1250	1			T54	12		T55	12		T101	13
lvl[1]	auto[1]	100	1			T9	2		T64	2		T65	2
lvl[4]	auto[0]	100	1			T54	1		T55	1		T101	1
lvl[8]	auto[0]	350	1			T54	3		T55	3		T101	4
lvl[16]	auto[0]	550	1			T54	5		T55	5		T101	6

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded