Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_acq_full.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_overflow.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_nak.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_tx_overflow.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_overflow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_nak.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_overflow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtilvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_nak.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_tx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_tx_stretch.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_acq_full.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_nak.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtilvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_nak.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_tx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01CoveredT27,T28,T33
10CoveredT26,T27,T28 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT27,T28,T33
11CoveredT27,T28,T33 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT27,T28,T33 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T28
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_nak.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_full.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_start.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_stop.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_readb.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_rcont.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_nakok.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T28 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T28 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T28
Cond Coverage for Module : prim_subreg_arb ( parameter DW=31,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_thigh.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_tlow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_r.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_f.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask1.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_txdata.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtilvl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT26,T27,T28
01Unreachable
10CoveredT26,T27,T34 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT26,T27,T28
1CoveredT26,T27,T34
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T26,T27,T28
0 Covered T26,T27,T28

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%