Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.53	100.00	66.67	99.46			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	566438897	3180	0	0
ctrl_rd_A	566438897	2555	0	0
fifo_ctrl_rd_A	566438897	7940	0	0
host_timeout_ctrl_rd_A	566438897	1760	0	0
intr_enable_rd_A	566438897	5085	0	0
ovrd_rd_A	566438897	3575	0	0
target_id_rd_A	566438897	2720	0	0
timeout_ctrl_rd_A	566438897	1715	0	0
timing0_rd_A	566438897	1690	0	0
timing1_rd_A	566438897	2830	0	0
timing2_rd_A	566438897	2080	0	0
timing3_rd_A	566438897	2750	0	0
timing4_rd_A	566438897	1545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	3180	0	0
T29	1891	14	0	0
T30	6433	3	0	0
T31	6433	3	0	0
T32	5447	142	0	0
T37	1575	0	0	0
T52	18853	0	0	0
T53	2743	0	0	0
T74	5447	142	0	0
T75	0	3	0	0
T77	0	14	0	0
T78	0	14	0	0
T79	0	3	0	0
T83	2743	0	0	0
T84	1367	0	0	0
T97	0	14	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	2555	0	0
T26	2743	23	0	0
T27	18853	163	0	0
T28	1367	0	0	0
T29	1891	14	0	0
T30	0	26	0	0
T32	0	8	0	0
T33	1367	0	0	0
T34	2743	23	0	0
T35	1367	0	0	0
T36	1575	6	0	0
T52	18853	163	0	0
T53	2743	23	0	0
T83	0	23	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	7940	0	0
T26	2743	2	0	0
T27	18853	150	0	0
T28	1367	0	0	0
T29	1891	0	0	0
T30	0	97	0	0
T31	0	97	0	0
T32	0	5	0	0
T33	1367	0	0	0
T34	2743	2	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	150	0	0
T53	2743	2	0	0
T74	0	5	0	0
T83	0	2	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	1760	0	0
T26	2743	10	0	0
T27	18853	167	0	0
T28	1367	0	0	0
T29	1891	0	0	0
T30	0	20	0	0
T31	0	20	0	0
T32	0	4	0	0
T33	1367	0	0	0
T34	2743	10	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	167	0	0
T53	2743	10	0	0
T74	0	4	0	0
T83	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	5085	0	0
T26	2743	7	0	0
T27	18853	167	0	0
T28	1367	14	0	0
T29	1891	1	0	0
T33	1367	14	0	0
T34	2743	7	0	0
T35	1367	14	0	0
T36	1575	0	0	0
T52	18853	167	0	0
T53	2743	7	0	0
T84	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	3575	0	0
T26	2743	5	0	0
T27	18853	160	0	0
T28	1367	0	0	0
T29	1891	4	0	0
T30	0	45	0	0
T31	0	45	0	0
T32	0	13	0	0
T33	1367	0	0	0
T34	2743	5	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	160	0	0
T53	2743	5	0	0
T83	0	5	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	2720	0	0
T26	2743	16	0	0
T27	18853	142	0	0
T28	1367	0	0	0
T29	1891	5	0	0
T30	0	45	0	0
T32	0	16	0	0
T33	1367	0	0	0
T34	2743	16	0	0
T35	1367	0	0	0
T36	1575	1	0	0
T52	18853	142	0	0
T53	2743	16	0	0
T83	0	16	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	1715	0	0
T26	2743	3	0	0
T27	18853	120	0	0
T28	1367	0	0	0
T29	1891	1	0	0
T30	0	41	0	0
T31	0	41	0	0
T32	0	5	0	0
T33	1367	0	0	0
T34	2743	3	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	120	0	0
T53	2743	3	0	0
T83	0	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	1690	0	0
T26	2743	6	0	0
T27	18853	128	0	0
T28	1367	0	0	0
T29	1891	6	0	0
T30	0	19	0	0
T31	0	19	0	0
T32	0	9	0	0
T33	1367	0	0	0
T34	2743	6	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	128	0	0
T53	2743	6	0	0
T83	0	6	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	2830	0	0
T26	2743	38	0	0
T27	18853	157	0	0
T28	1367	0	0	0
T29	1891	12	0	0
T30	0	31	0	0
T31	0	31	0	0
T32	0	10	0	0
T33	1367	0	0	0
T34	2743	38	0	0
T35	1367	0	0	0
T36	1575	0	0	0
T52	18853	157	0	0
T53	2743	38	0	0
T83	0	38	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	2080	0	0
T26	2743	9	0	0
T27	18853	141	0	0
T28	1367	0	0	0
T29	1891	3	0	0
T30	0	23	0	0
T32	0	10	0	0
T33	1367	0	0	0
T34	2743	9	0	0
T35	1367	0	0	0
T36	1575	15	0	0
T52	18853	141	0	0
T53	2743	9	0	0
T83	0	9	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	2750	0	0
T26	2743	22	0	0
T27	18853	137	0	0
T28	1367	0	0	0
T29	1891	9	0	0
T30	0	45	0	0
T32	0	16	0	0
T33	1367	0	0	0
T34	2743	22	0	0
T35	1367	0	0	0
T36	1575	4	0	0
T52	18853	137	0	0
T53	2743	22	0	0
T83	0	22	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566438897	1545	0	0
T26	2743	2	0	0
T27	18853	165	0	0
T28	1367	0	0	0
T29	1891	3	0	0
T30	0	20	0	0
T32	0	1	0	0
T33	1367	0	0	0
T34	2743	2	0	0
T35	1367	0	0	0
T36	1575	4	0	0
T52	18853	165	0	0
T53	2743	2	0	0
T83	0	2	0	0