Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	99.07	96.59	100.00	96.52	98.13	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	96.91	98.84	92.32		96.52	96.88	100.00
i2c_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.58	99.26	99.44	100.00		99.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
127	1	1
128	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T86,T87,T88
1	0	Covered	T1,T2,T3
1	1	Covered	T86,T87,T88

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	45	45	100.00
Total Bits	370	370	100.00
Total Bits 0->1	185	185	100.00
Total Bits 1->0	185	185	100.00

Ports	45	45	100.00
Port Bits	370	370	100.00
Port Bits 0->1	185	185	100.00
Port Bits 1->0	185	185	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
rst_ni	Yes	Yes	T21,T23,T73	Yes	T19,T20,T21	INPUT
tl_i.d_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_address[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_source[7:0]	Yes	Yes	T19,T21,T22	Yes	T19,T20,T21	INPUT
tl_i.a_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_o.a_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T19,*T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T19,T21,T22	Yes	T19,T20,T21	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T19,*T20,*T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T23,T25	Yes	T21,T23,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T23,T25	Yes	T21,T23,T25	OUTPUT
cio_scl_i	Yes	Yes	T21,T23,T26	Yes	T21,T23,T73	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T21,T23,T73	Yes	T21,T23,T26	OUTPUT
cio_sda_i	Yes	Yes	T21,T23,T26	Yes	T21,T23,T26	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T21,T23,T26	Yes	T21,T23,T26	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T24,T27,T89	Yes	T24,T27,T89	OUTPUT
intr_rx_threshold_o	Yes	Yes	T19,T20,T90	Yes	T19,T20,T90	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T19,T24,T27	Yes	T19,T24,T27	OUTPUT
intr_rx_overflow_o	Yes	Yes	T20,T27,T61	Yes	T20,T27,T61	OUTPUT
intr_nak_o	Yes	Yes	T19,T20,T24	Yes	T19,T20,T24	OUTPUT
intr_scl_interference_o	Yes	Yes	T20,T24,T27	Yes	T20,T24,T27	OUTPUT
intr_sda_interference_o	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T20,T24,T61	Yes	T20,T24,T61	OUTPUT
intr_sda_unstable_o	Yes	Yes	T19,T24,T27	Yes	T19,T24,T27	OUTPUT
intr_cmd_complete_o	Yes	Yes	T19,T20,T61	Yes	T19,T20,T61	OUTPUT
intr_tx_stretch_o	Yes	Yes	T19,T24,T27	Yes	T19,T24,T27	OUTPUT
intr_tx_overflow_o	Yes	Yes	T19,T24,T61	Yes	T19,T24,T61	OUTPUT
intr_acq_full_o	Yes	Yes	T19,T20,T27	Yes	T19,T20,T27	OUTPUT
intr_unexp_stop_o	Yes	Yes	T19,T20,T24	Yes	T19,T20,T24	OUTPUT
intr_host_timeout_o	Yes	Yes	T19,T24,T89	Yes	T19,T24,T89	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	495209351	495021327	0	0
CioSclEnKnownO_A	495209351	495021327	0	0
CioSclKnownO_A	495209351	495021327	0	0
CioSdaEnKnownO_A	495209351	495021327	0	0
CioSdaKnownO_A	495209351	495021327	0	0
FpvSecCmRegWeOnehotCheck_A	495209351	80	0	0
IntrAcqFulllwKnownO_A	495209351	495021327	0	0
IntrCommandCompleteKnownO_A	495209351	495021327	0	0
IntrFmtOflwKnownO_A	495209351	495021327	0	0
IntrFmtWtmkKnownO_A	495209351	495021327	0	0
IntrHostTimeoutKnownO_A	495209351	495021327	0	0
IntrNakKnownO_A	495209351	495021327	0	0
IntrRxOflwKnownO_A	495209351	495021327	0	0
IntrRxWtmkKnownO_A	495209351	495021327	0	0
IntrSclInterfKnownO_A	495209351	495021327	0	0
IntrSdaInterfKnownO_A	495209351	495021327	0	0
IntrSdaUnstableKnownO_A	495209351	495021327	0	0
IntrStretchTimeoutKnownO_A	495209351	495021327	0	0
IntrTxOflwKnownO_A	495209351	495021327	0	0
IntrTxStretchKnownO_A	495209351	495021327	0	0
IntrUnexpStopKnownO_A	495209351	495021327	0	0
TlAReadyKnownO_A	495209351	495021327	0	0
TlDValidKnownO_A	495209351	495021327	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	80	0	0
T70	3574	10	0	0
T71	6260	20	0	0
T72	0	20	0	0
T88	1031	0	0	0
T91	0	10	0	0
T92	0	20	0	0
T93	124965	0	0	0
T94	278520	0	0	0
T95	95681	0	0	0
T96	496339	0	0	0
T97	37164	0	0	0
T98	96959	0	0	0
T99	580077	0	0	0

IntrAcqFulllwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrFmtOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrNakKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrTxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0