Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	495833896	52754	0	0
ctrl_rd_A	495833896	1240	0	0
fifo_ctrl_rd_A	495833896	4217	0	0
host_timeout_ctrl_rd_A	495833896	1007	0	0
intr_enable_rd_A	495833896	3953	0	0
ovrd_rd_A	495833896	1974	0	0
target_id_rd_A	495833896	1469	0	0
timeout_ctrl_rd_A	495833896	1118	0	0
timing0_rd_A	495833896	1255	0	0
timing1_rd_A	495833896	1131	0	0
timing2_rd_A	495833896	1138	0	0
timing3_rd_A	495833896	1155	0	0
timing4_rd_A	495833896	1215	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	52754	0	0
T21	8214	7	0	0
T22	14499	939	0	0
T23	4509	2	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	355	0	0
T61	1100	0	0	0
T69	0	372	0	0
T73	6866	2	0	0
T74	0	327	0	0
T75	0	8315	0	0
T77	0	9	0	0
T81	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1240	0	0
T22	14499	27	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	14	0	0
T61	1100	0	0	0
T73	6866	89	0	0
T77	0	157	0	0
T83	0	161	0	0
T101	0	11	0	0
T103	2223	0	0	0
T118	0	15	0	0
T126	0	4	0	0
T127	0	209	0	0
T128	0	3	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	4217	0	0
T22	14499	10	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	15	0	0
T61	1100	0	0	0
T73	6866	122	0	0
T77	0	272	0	0
T103	2223	0	0	0
T105	0	6	0	0
T124	0	119	0	0
T129	0	88	0	0
T130	0	129	0	0
T131	0	105	0	0
T132	0	103	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1007	0	0
T22	14499	18	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	0	0	0
T61	1100	0	0	0
T73	6866	40	0	0
T77	0	65	0	0
T83	0	84	0	0
T101	0	16	0	0
T103	2223	0	0	0
T105	0	13	0	0
T118	0	2	0	0
T126	0	10	0	0
T127	0	226	0	0
T128	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	3953	0	0
T3	0	5	0	0
T19	1702	10	0	0
T20	1896	0	0	0
T21	8214	0	0	0
T22	14499	14	0	0
T23	4509	0	0	0
T24	1340	8	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	4	0	0
T30	0	19	0	0
T73	0	324	0	0
T77	0	651	0	0
T105	0	11	0	0
T123	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1974	0	0
T6	0	51	0	0
T22	14499	21	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	9	0	0
T61	1100	0	0	0
T73	6866	66	0	0
T77	0	159	0	0
T103	2223	0	0	0
T105	0	49	0	0
T133	0	33	0	0
T134	0	33	0	0
T135	0	58	0	0
T136	0	35	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1469	0	0
T22	14499	4	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	0	0	0
T61	1100	0	0	0
T73	6866	90	0	0
T77	0	208	0	0
T83	0	133	0	0
T101	0	43	0	0
T103	2223	0	0	0
T105	0	16	0	0
T118	0	11	0	0
T126	0	6	0	0
T127	0	208	0	0
T128	0	17	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1118	0	0
T22	14499	16	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	0	0	0
T61	1100	0	0	0
T73	6866	67	0	0
T77	0	91	0	0
T83	0	94	0	0
T101	0	5	0	0
T103	2223	0	0	0
T105	0	45	0	0
T118	0	21	0	0
T126	0	14	0	0
T127	0	186	0	0
T128	0	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1255	0	0
T22	14499	4	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	7	0	0
T61	1100	0	0	0
T73	6866	45	0	0
T77	0	94	0	0
T83	0	109	0	0
T101	0	2	0	0
T103	2223	0	0	0
T105	0	31	0	0
T118	0	12	0	0
T126	0	17	0	0
T127	0	269	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1131	0	0
T22	14499	16	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	0	0	0
T61	1100	0	0	0
T73	6866	66	0	0
T77	0	119	0	0
T83	0	116	0	0
T101	0	3	0	0
T103	2223	0	0	0
T105	0	7	0	0
T118	0	4	0	0
T126	0	8	0	0
T127	0	219	0	0
T128	0	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1138	0	0
T22	14499	20	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	0	0	0
T61	1100	0	0	0
T73	6866	64	0	0
T77	0	101	0	0
T83	0	117	0	0
T101	0	1	0	0
T103	2223	0	0	0
T105	0	35	0	0
T118	0	4	0	0
T126	0	12	0	0
T127	0	217	0	0
T128	0	9	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1155	0	0
T22	14499	19	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	9	0	0
T61	1100	0	0	0
T73	6866	55	0	0
T77	0	103	0	0
T83	0	82	0	0
T101	0	3	0	0
T103	2223	0	0	0
T105	0	13	0	0
T118	0	5	0	0
T126	0	19	0	0
T127	0	220	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495833896	1215	0	0
T22	14499	3	0	0
T23	4509	0	0	0
T24	1340	0	0	0
T25	1491	0	0	0
T26	1575	0	0	0
T27	1366	0	0	0
T28	5272	5	0	0
T61	1100	0	0	0
T73	6866	59	0	0
T77	0	101	0	0
T83	0	117	0	0
T101	0	6	0	0
T103	2223	0	0	0
T105	0	9	0	0
T118	0	54	0	0
T126	0	13	0	0
T127	0	199	0	0