0c759b93ab| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.805m | 2.817ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.410s | 28.427ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 47.898us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.710s | 19.729us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.040s | 1.548ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.330s | 190.771us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.520s | 30.954us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.710s | 19.729us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.330s | 190.771us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.920s | 82.719us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 54.340m | 71.283ms | 29 | 50 | 58.00 |
| V2 | host_perf | i2c_host_perf | 23.593m | 28.940ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.680s | 18.926us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 13.472m | 6.554ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 14.716m | 10.650ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.150s | 621.735us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.640s | 616.019us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 17.960s | 1.360ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.709m | 3.904ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 49.480s | 15.775ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 6.001m | 3.186ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 4.308m | 3.103ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.770s | 9.584ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.700s | 2.189ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.957m | 83.397ms | 40 | 50 | 80.00 |
| V2 | target_perf | i2c_target_perf | 5.130s | 3.875ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 4.458m | 3.841ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.435m | 7.474ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.340s | 2.140ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.246m | 10.139ms | 49 | 50 | 98.00 |
| i2c_target_fifo_reset_tx | 1.627m | 10.088ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 53.058m | 48.586ms | 41 | 50 | 82.00 |
| i2c_target_stress_rd | 1.435m | 7.474ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 29.229m | 65.262ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.710s | 37.670ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 50.591m | 43.889ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.770s | 3.995ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.470s | 835.398us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.680s | 46.298us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 22.229us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.750s | 148.166us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.750s | 148.166us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 47.898us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.710s | 19.729us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 190.771us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.960s | 80.863us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 47.898us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.710s | 19.729us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 190.771us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.960s | 80.863us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1443 | 1492 | 96.72 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.890s | 112.142us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.740s | 2.113ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.890s | 112.142us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 15.486m | 57.443ms | 3 | 50 | 6.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.364m | 72.870ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 3 | 100 | 3.00 | |||
| TOTAL | 1626 | 1772 | 91.76 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 25 | 78.12 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.60 | 99.07 | 96.59 | 100.00 | 96.52 | 98.13 | 100.00 | 92.86 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 103 failures:
0.i2c_host_stress_all.41572733070993764737850448040897346890279906082445225233977826219115172287391
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:efa5458d-e4de-4e18-a2b0-8733e4302ae0
5.i2c_host_stress_all.49263616361844646949437839713196251162689174960719000800649883402793233615436
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:edda89b1-3b57-4dbb-9493-9ce39f448aab
... and 19 more failures.
0.i2c_host_stress_all_with_rand_reset.26676199651494792098806380599689060832379836255054803546340382198384926039493
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b0c90366-4296-4922-a0c6-ce26facd4685
1.i2c_host_stress_all_with_rand_reset.37328175636437106297829498074519236817174692483963254311238494836734527703406
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2ded27a5-74ed-48bc-bd28-5c903fb684f8
... and 45 more failures.
4.i2c_target_stress_all.66315586044075731094694542786385217022755778670790462416321546803589180579437
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
Job ID: smart:f1fc0874-3011-403b-b669-acd39050f6f9
5.i2c_target_stress_all.75533523487242243662971238021514365223905904006088873114192913912388693215323
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Job ID: smart:58abe8cd-7b4b-463c-bc10-66a09b40ebc5
... and 8 more failures.
5.i2c_target_stress_wr.72338339347386705809534261584960619922692135055051620912175042160692086820238
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_wr/latest/run.log
Job ID: smart:fdcb92d2-68a8-41da-826a-7ddccabf3758
8.i2c_target_stress_wr.44623898742144833694080242943392647238724493319856339669417643297307064285238
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest/run.log
Job ID: smart:726c2666-e022-40b7-a072-aa500e8915d8
... and 7 more failures.
5.i2c_target_stress_all_with_rand_reset.40038322489681004520764039075632331875988745721051848740849449705353188025770
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:deb0908d-f659-4864-a941-94199e87a554
6.i2c_target_stress_all_with_rand_reset.70163598287839245759701087373213965326413111615491831797228593782679015826973
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d1c8cd65-e466-4dfe-acb3-21fd6f41f4cb
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 16 failures:
2.i2c_target_stress_all_with_rand_reset.52846569491076273648655001365028263263689516419353162500460038635653149538123
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21728451844 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (12 [0xc] vs 3 [0x3])
UVM_INFO @ 21728451844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.50163733545316371180227188689608180003487838097575365115194624991752384353968
Line 350, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27829448535 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 12 [0xc])
UVM_INFO @ 27829448535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 10 failures:
17.i2c_target_stress_all_with_rand_reset.3755893708902145047514439382369148190685030985408491124462773272656019537362
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33524437 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 33524437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all_with_rand_reset.7216150645840761433646726141038742733171502187781553097371942853071383059576
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2544939848 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2544939848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 7 failures:
0.i2c_target_stress_all_with_rand_reset.47296135877747122011677919106361138168825984483499999998454676311060975456042
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2821092706 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8265a794) == 0x0
UVM_INFO @ 2821092706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.89459254553358377673211543124946925917894273892841772302729611733237037072955
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2515328002 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x50caaa14) == 0x0
UVM_INFO @ 2515328002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 4 failures:
1.i2c_target_stress_all_with_rand_reset.64234882403928944168079067779596048752909549849598911031489542181174002996451
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 365346746 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (164 [0xa4] vs 82 [0x52])
UVM_INFO @ 365346746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.105970061536101782636231605251684189263128852858378041698815338890891964585955
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 83362977 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (46 [0x2e] vs 204 [0xcc])
UVM_INFO @ 83362977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending 'scl_i' has 2 failures:
7.i2c_target_stress_all_with_rand_reset.88145340110338341863260756452449868675634290794643712909309092490716104665892
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 1231190138 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 1231190138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stress_all_with_rand_reset.13410049095095275233425192755244512558990527010914078936050164452577039942818
Line 301, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 9237132784 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 9237132784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_fifo_reset_acq has 1 failures.
16.i2c_target_fifo_reset_acq.114735440301213879756464248939538033539565011579039552123536352496534295673418
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_bad_addr has 1 failures.
48.i2c_target_bad_addr.63204591447123987582975919858575375528380174467155970834452047425268215150990
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 1 failures:
26.i2c_target_stress_all_with_rand_reset.73711992778757787040243482131118638834330541448673313956580505496119840466612
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 848945468 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 848945468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 1 failures:
41.i2c_target_stress_all_with_rand_reset.73041483725783555258048900103437369345415094214034013000636489590764488117052
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77060278 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 77060278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---