Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	536229817	94369	0	0
ctrl_rd_A	536229817	3805	0	0
fifo_ctrl_rd_A	536229817	6801	0	0
host_timeout_ctrl_rd_A	536229817	3109	0	0
intr_enable_rd_A	536229817	5157	0	0
ovrd_rd_A	536229817	4544	0	0
target_id_rd_A	536229817	3761	0	0
timeout_ctrl_rd_A	536229817	3268	0	0
timing0_rd_A	536229817	3470	0	0
timing1_rd_A	536229817	3185	0	0
timing2_rd_A	536229817	3757	0	0
timing3_rd_A	536229817	3085	0	0
timing4_rd_A	536229817	3614	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	94369	0	0
T17	5257	373	0	0
T18	9807	7	0	0
T19	1268	0	0	0
T20	40794	0	0	0
T21	11384	3	0	0
T22	5817	3	0	0
T23	2106	32	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T76	0	452	0	0
T80	0	421	0	0
T85	0	3	0	0
T86	0	5	0	0
T89	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3805	0	0
T20	40794	415	0	0
T21	11384	119	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	352	0	0
T76	6410	0	0	0
T82	0	258	0	0
T92	1302	0	0	0
T104	0	826	0	0
T106	1819	0	0	0
T107	0	979	0	0
T108	0	36	0	0
T113	0	84	0	0
T131	0	24	0	0
T132	0	12	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	6801	0	0
T20	40794	463	0	0
T21	11384	342	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T76	6410	0	0	0
T80	0	4	0	0
T92	1302	0	0	0
T106	1819	0	0	0
T133	0	113	0	0
T134	0	91	0	0
T135	0	33	0	0
T136	0	50	0	0
T137	0	65	0	0
T138	0	97	0	0
T139	0	87	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3109	0	0
T20	40794	484	0	0
T21	11384	125	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	320	0	0
T76	6410	0	0	0
T80	0	2	0	0
T82	0	194	0	0
T92	1302	0	0	0
T104	0	597	0	0
T106	1819	0	0	0
T107	0	705	0	0
T108	0	17	0	0
T131	0	5	0	0
T132	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	5157	0	0
T20	40794	465	0	0
T21	11384	696	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	3	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	342	0	0
T69	0	11	0	0
T76	6410	0	0	0
T80	0	2	0	0
T82	0	243	0	0
T92	1302	0	0	0
T106	1819	0	0	0
T140	0	12	0	0
T141	0	32	0	0
T142	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	4544	0	0
T4	0	37	0	0
T6	0	40	0	0
T20	40794	515	0	0
T21	11384	157	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T76	6410	0	0	0
T80	0	17	0	0
T92	1302	0	0	0
T106	1819	0	0	0
T143	0	45	0	0
T144	0	33	0	0
T145	0	57	0	0
T146	0	52	0	0
T147	0	49	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3761	0	0
T20	40794	431	0	0
T21	11384	134	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	403	0	0
T76	6410	0	0	0
T80	0	4	0	0
T82	0	202	0	0
T92	1302	0	0	0
T104	0	793	0	0
T106	1819	0	0	0
T107	0	969	0	0
T108	0	29	0	0
T131	0	24	0	0
T132	0	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3268	0	0
T20	40794	437	0	0
T21	11384	103	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	365	0	0
T76	6410	0	0	0
T80	0	18	0	0
T82	0	181	0	0
T92	1302	0	0	0
T104	0	658	0	0
T106	1819	0	0	0
T107	0	836	0	0
T108	0	14	0	0
T131	0	16	0	0
T132	0	7	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3470	0	0
T20	40794	411	0	0
T21	11384	92	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	423	0	0
T76	6410	0	0	0
T80	0	5	0	0
T82	0	201	0	0
T92	1302	0	0	0
T104	0	662	0	0
T106	1819	0	0	0
T107	0	909	0	0
T108	0	40	0	0
T131	0	21	0	0
T132	0	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3185	0	0
T20	40794	492	0	0
T21	11384	88	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	303	0	0
T76	6410	0	0	0
T80	0	11	0	0
T82	0	263	0	0
T92	1302	0	0	0
T104	0	659	0	0
T106	1819	0	0	0
T107	0	745	0	0
T108	0	22	0	0
T131	0	12	0	0
T132	0	3	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3757	0	0
T20	40794	424	0	0
T21	11384	102	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	407	0	0
T76	6410	0	0	0
T80	0	13	0	0
T82	0	292	0	0
T92	1302	0	0	0
T104	0	759	0	0
T106	1819	0	0	0
T107	0	998	0	0
T108	0	28	0	0
T131	0	24	0	0
T132	0	12	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3085	0	0
T20	40794	415	0	0
T21	11384	124	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	305	0	0
T76	6410	0	0	0
T80	0	5	0	0
T82	0	247	0	0
T92	1302	0	0	0
T104	0	598	0	0
T106	1819	0	0	0
T107	0	713	0	0
T108	0	38	0	0
T131	0	32	0	0
T132	0	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536229817	3614	0	0
T20	40794	440	0	0
T21	11384	122	0	0
T22	5817	0	0	0
T23	2106	0	0	0
T24	1843	0	0	0
T25	2918	0	0	0
T26	1990	0	0	0
T43	0	295	0	0
T76	6410	0	0	0
T82	0	351	0	0
T92	1302	0	0	0
T104	0	684	0	0
T106	1819	0	0	0
T107	0	997	0	0
T108	0	33	0	0
T113	0	85	0	0
T131	0	24	0	0
T132	0	12	0	0