Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

226172

1

T2

188

T3

80

T10

488

ack

19488

1

T2

12

T3

1

T9

37

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	869	1			T2	2		T10	4		T36	5
high	50011	1			T2	52		T3	18		T9	4
med	91552	1			T2	75		T3	24		T9	9
sml	102266	1			T2	70		T3	39		T9	24
all_zero	962	1			T2	1		T10	1		T36	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122581

1

T2

96

T3

41

T9

20

auto[1]

123079

1

T2

104

T3

40

T9

17

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167984

1

T2

121

T3

53

T9

29

auto[1]

77676

1

T2

79

T3

28

T9

8

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234545

1

T2

200

T3

81

T9

15

auto[1]

11115

1

T9

22

T10

82

T11

16

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231587

1

T2

188

T3

80

T9

22

auto[1]

14073

1

T2

12

T3

1

T9

15

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233400

1

T2

188

T3

80

T9

23

auto[1]

12260

1

T2

12

T3

1

T9

14

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122581

1

T2

96

T3

41

T9

20

auto[1]

123079

1

T2

104

T3

40

T9

17

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167984

1

T2

121

T3

53

T9

29

auto[1]

77676

1

T2

79

T3

28

T9

8

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234545

1

T2

200

T3

81

T9

15

auto[1]

11115

1

T9

22

T10

82

T11

16

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231587

1

T2

188

T3

80

T9

22

auto[1]

14073

1

T2

12

T3

1

T9

15

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233400

1

T2

188

T3

80

T9

23

auto[1]

12260

1

T2

12

T3

1

T9

14

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T177

1

T137

1

T178

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T129

1

T179

1

T180

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T181

1

T141

1

T182

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

575

1

T10

10

T12

2

T37

4

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

287

1

T10

1

T37

2

T183

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

293

1

T10

2

T12

1

T13

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1178

1

T10

8

T36

1

T13

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

567

1

T10

5

T12

1

T13

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

606

1

T10

4

T13

2

T37

5

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1078

1

T10

5

T12

4

T13

7

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

575

1

T10

3

T36

1

T12

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

537

1

T10

4

T12

1

T13

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T12

1

T13

1

T129

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

10

1

T47

1

T184

1

T182

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T185

1

T50

1

T186

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	71234	1			T2	44		T3	26		T10	118
write_address_byte	14073	1			T2	12		T3	1		T9	15
read_with_ack	3867	1			T9	8		T10	35		T11	5
read_with_nack	7248	1			T9	14		T10	47		T11	11
stop_byte	12260	1			T2	12		T3	1		T9	14
write_address_byte_nak	9015	1			T10	77		T36	4		T12	16
data_byte_nack	226172	1			T2	188		T3	80		T10	488
stop_byte_nack	8611	1			T2	12		T3	1		T10	62
nakok_byte_nack	113353	1			T2	97		T3	40		T10	254
nakok_addr_byte_nack	4522	1			T10	36		T36	4		T12	7