Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46660305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16378382

1

T17

193

T18

396

T19

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55940474	1			T17	62		T18	681		T19	20
values[0x0]	3547690	1			T17	69		T18	227		T19	9
values[0x1]	3550523	1			T17	92		T18	180		T19	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34339105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28699582

1

T17

211

T18

623

T19

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	313012	1			T20	22		T21	4		T106	1
valid_sources[0x01]	203440	1			T20	22		T21	6		T92	1
valid_sources[0x02]	243179	1			T20	14		T21	7		T22	1
valid_sources[0x03]	204304	1			T17	2		T20	10		T21	2
valid_sources[0x04]	227089	1			T17	1		T20	12		T21	3
valid_sources[0x05]	216737	1			T20	9		T21	3		T22	2
valid_sources[0x06]	291034	1			T20	21		T21	5		T22	3
valid_sources[0x07]	248785	1			T17	2		T20	16		T21	5
valid_sources[0x08]	244830	1			T17	2		T18	13		T20	19
valid_sources[0x09]	225712	1			T18	5		T20	10		T21	3
valid_sources[0x0a]	744683	1			T20	17		T21	4		T22	2
valid_sources[0x0b]	214458	1			T17	1		T20	15		T21	3
valid_sources[0x0c]	228110	1			T17	1		T18	26		T20	13
valid_sources[0x0d]	202863	1			T17	2		T20	15		T21	6
valid_sources[0x0e]	213991	1			T20	21		T21	6		T22	2
valid_sources[0x0f]	201872	1			T17	3		T20	22		T21	5
valid_sources[0x10]	217642	1			T18	21		T20	17		T22	7
valid_sources[0x11]	205864	1			T18	1		T20	9		T21	3
valid_sources[0x12]	221817	1			T17	4		T20	14		T21	5
valid_sources[0x13]	223532	1			T17	2		T20	16		T21	5
valid_sources[0x14]	222483	1			T17	4		T20	19		T21	5
valid_sources[0x15]	232000	1			T17	2		T18	1		T20	20
valid_sources[0x16]	235424	1			T17	1		T20	14		T21	4
valid_sources[0x17]	215994	1			T17	1		T20	13		T21	5
valid_sources[0x18]	230212	1			T20	12		T21	3		T22	3
valid_sources[0x19]	378531	1			T17	2		T20	10		T21	3
valid_sources[0x1a]	225450	1			T18	5		T20	16		T21	2
valid_sources[0x1b]	223184	1			T20	16		T21	1		T22	3
valid_sources[0x1c]	229965	1			T18	8		T20	15		T21	4
valid_sources[0x1d]	243248	1			T17	1		T20	8		T21	4
valid_sources[0x1e]	208178	1			T20	14		T21	2		T22	5
valid_sources[0x1f]	230959	1			T17	1		T18	4		T20	18
valid_sources[0x20]	214500	1			T20	23		T21	2		T22	6
valid_sources[0x21]	208655	1			T20	10		T21	3		T106	1
valid_sources[0x22]	233422	1			T20	12		T21	5		T106	3
valid_sources[0x23]	255601	1			T20	17		T21	6		T92	1
valid_sources[0x24]	216491	1			T17	1		T20	12		T21	2
valid_sources[0x25]	220027	1			T17	1		T20	12		T21	4
valid_sources[0x26]	225997	1			T20	16		T21	5		T86	7
valid_sources[0x27]	231616	1			T17	2		T18	6		T20	16
valid_sources[0x28]	226075	1			T20	15		T21	5		T22	1
valid_sources[0x29]	210275	1			T18	6		T20	13		T21	4
valid_sources[0x2a]	216329	1			T17	3		T18	10		T20	16
valid_sources[0x2b]	354582	1			T17	2		T18	11		T20	16
valid_sources[0x2c]	212874	1			T20	12		T21	10		T22	2
valid_sources[0x2d]	222136	1			T17	1		T20	18		T21	3
valid_sources[0x2e]	206558	1			T17	3		T20	15		T21	2
valid_sources[0x2f]	222199	1			T17	1		T18	3		T20	15
valid_sources[0x30]	219354	1			T20	23		T21	4		T22	3
valid_sources[0x31]	231345	1			T18	38		T19	40		T20	14
valid_sources[0x32]	997886	1			T17	1		T18	12		T20	13
valid_sources[0x33]	217852	1			T17	1		T20	25		T21	1
valid_sources[0x34]	220027	1			T20	10		T21	8		T22	3
valid_sources[0x35]	236927	1			T18	13		T20	14		T21	2
valid_sources[0x36]	214735	1			T18	10		T20	18		T21	4
valid_sources[0x37]	206344	1			T18	33		T20	11		T21	8
valid_sources[0x38]	239099	1			T17	8		T20	16		T21	7
valid_sources[0x39]	245289	1			T17	1		T18	18		T20	14
valid_sources[0x3a]	258155	1			T18	23		T20	15		T21	4
valid_sources[0x3b]	246499	1			T17	1		T20	20		T21	2
valid_sources[0x3c]	227577	1			T20	14		T21	1		T92	1
valid_sources[0x3d]	239086	1			T17	1		T20	12		T21	3
valid_sources[0x3e]	262354	1			T20	19		T21	3		T22	2
valid_sources[0x3f]	219648	1			T17	2		T20	18		T21	3
valid_sources[0x40]	211227	1			T17	2		T20	8		T21	5
valid_sources[0x41]	228343	1			T20	17		T21	7		T22	3
valid_sources[0x42]	214853	1			T20	10		T21	4		T22	2
valid_sources[0x43]	214838	1			T17	1		T18	7		T20	18
valid_sources[0x44]	237241	1			T17	3		T18	3		T20	10
valid_sources[0x45]	250976	1			T20	11		T21	2		T22	3
valid_sources[0x46]	253019	1			T17	3		T20	11		T21	6
valid_sources[0x47]	223329	1			T17	2		T20	15		T21	2
valid_sources[0x48]	214100	1			T17	3		T18	8		T20	13
valid_sources[0x49]	220026	1			T17	1		T20	11		T21	4
valid_sources[0x4a]	232055	1			T18	9		T20	14		T21	2
valid_sources[0x4b]	235751	1			T20	16		T21	1		T22	4
valid_sources[0x4c]	335734	1			T17	1		T20	19		T21	1
valid_sources[0x4d]	224197	1			T17	2		T20	13		T21	2
valid_sources[0x4e]	252903	1			T20	10		T21	1		T22	4
valid_sources[0x4f]	218985	1			T18	1		T20	10		T21	3
valid_sources[0x50]	207806	1			T20	11		T21	1		T106	1
valid_sources[0x51]	247587	1			T20	12		T21	4		T22	3
valid_sources[0x52]	397114	1			T17	1		T20	9		T21	4
valid_sources[0x53]	246177	1			T20	13		T21	6		T22	6
valid_sources[0x54]	218686	1			T17	1		T20	11		T21	4
valid_sources[0x55]	231468	1			T17	1		T18	16		T20	15
valid_sources[0x56]	235364	1			T20	19		T21	1		T106	1
valid_sources[0x57]	217297	1			T17	2		T20	8		T21	4
valid_sources[0x58]	229735	1			T17	3		T20	14		T21	2
valid_sources[0x59]	233770	1			T17	3		T20	18		T21	5
valid_sources[0x5a]	224427	1			T17	2		T18	7		T20	10
valid_sources[0x5b]	256487	1			T20	18		T21	6		T22	1
valid_sources[0x5c]	243680	1			T17	2		T20	8		T21	5
valid_sources[0x5d]	245393	1			T17	1		T20	15		T21	4
valid_sources[0x5e]	223682	1			T18	26		T20	18		T21	7
valid_sources[0x5f]	213430	1			T17	1		T20	10		T21	5
valid_sources[0x60]	234018	1			T20	18		T21	7		T22	7
valid_sources[0x61]	363394	1			T20	13		T21	7		T22	3
valid_sources[0x62]	247513	1			T17	3		T20	12		T21	6
valid_sources[0x63]	228782	1			T17	1		T18	8		T20	18
valid_sources[0x64]	209544	1			T20	18		T21	5		T22	1
valid_sources[0x65]	240668	1			T17	2		T18	46		T20	12
valid_sources[0x66]	230348	1			T20	11		T21	10		T22	2
valid_sources[0x67]	231837	1			T20	11		T21	2		T22	1
valid_sources[0x68]	351006	1			T17	1		T20	15		T21	1
valid_sources[0x69]	233562	1			T17	1		T20	14		T21	4
valid_sources[0x6a]	251850	1			T20	13		T21	7		T92	1
valid_sources[0x6b]	230426	1			T17	3		T18	2		T20	23
valid_sources[0x6c]	209055	1			T17	2		T20	19		T21	4
valid_sources[0x6d]	234037	1			T17	1		T18	22		T20	15
valid_sources[0x6e]	357248	1			T20	15		T21	3		T25	1
valid_sources[0x6f]	217354	1			T17	3		T20	17		T21	2
valid_sources[0x70]	236793	1			T20	15		T21	2		T92	1
valid_sources[0x71]	238212	1			T17	1		T20	12		T21	6
valid_sources[0x72]	250814	1			T20	12		T21	4		T22	2
valid_sources[0x73]	203483	1			T17	1		T20	8		T21	5
valid_sources[0x74]	212777	1			T18	4		T20	16		T21	7
valid_sources[0x75]	256732	1			T20	19		T21	7		T22	5
valid_sources[0x76]	232248	1			T20	13		T21	4		T22	3
valid_sources[0x77]	249920	1			T17	1		T18	12		T20	19
valid_sources[0x78]	283695	1			T18	14		T20	12		T21	2
valid_sources[0x79]	202332	1			T20	24		T21	8		T92	1
valid_sources[0x7a]	228179	1			T17	1		T20	13		T21	5
valid_sources[0x7b]	255321	1			T20	17		T21	5		T25	4
valid_sources[0x7c]	207337	1			T17	2		T20	13		T21	2
valid_sources[0x7d]	200664	1			T17	2		T20	19		T21	3
valid_sources[0x7e]	221385	1			T17	2		T20	14		T21	5
valid_sources[0x7f]	212797	1			T18	5		T20	14		T21	10
valid_sources[0x80]	311013	1			T20	15		T21	5		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13662549

1

T17

53

T18

101

T19

9

values[0x0]

all_enables

biggest_size

1744483

1

T17

68

T18

169

T19

5

values[0x1]

all_enables

biggest_size

971350

1

T17

72

T18

126

T19

1