Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_level_cg

Group : i2c_env_pkg::i2c_fifo_level_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	94.12	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.rx_fifo_level_cg	88.24	1	100	1	64	64
i2c_env_pkg.fmt_fifo_level_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	2	6	75.00

Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	2	6	75.00	100	1	1	0

---

Group Instance : i2c_env_pkg.fmt_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	0	8	100.00	100	1	1	0

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	33309	1			T1	7		T2	13		T3	2
lvl[1]	203	1			T75	4		T183	4		T30	2
lvl[4]	160	1			T75	2		T183	1		T30	3
lvl[8]	174	1			T75	2		T183	1		T30	13
lvl[16]	153	1			T75	3		T183	4		T30	2

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30157

1

T1

7

T2

13

T3

2

auto[1]

3842

1

T36

5

T12

22

T73

2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31385

1

T1

6

T2

12

T3

1

auto[1]

2614

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	2	6	75.00	2
Automatically Generated Cross Bins	8	2	6	75.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[4]]	[auto[1]]	0	1	1
[lvl[16]]	[auto[1]]	0	1	1

Covered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	158	1			T75	4		T183	4		T30	2
lvl[1]	auto[1]	45	1			T142	21		T197	24		-	-
lvl[4]	auto[0]	160	1			T75	2		T183	1		T30	3
lvl[8]	auto[0]	165	1			T75	2		T183	1		T30	4
lvl[8]	auto[1]	9	1			T30	9		-	-		-	-
lvl[16]	auto[0]	153	1			T75	3		T183	4		T30	2

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	31600	1			T1	7		T2	13		T3	2
lvl[1]	1345	1			T75	14		T51	10		T52	4
lvl[4]	345	1			T75	4		T51	2		T52	2
lvl[8]	402	1			T75	3		T183	5		T30	7
lvl[16]	307	1			T75	1		T183	4		T30	3

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27969

1

T1

7

T2

2

T3

2

auto[1]

6030

1

T2

11

T44

16

T36

9

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31040

1

T1

6

T2

12

T3

1

auto[1]

2959

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	1116	1			T75	14		T51	2		T183	19
lvl[1]	auto[1]	229	1			T51	8		T52	4		T30	7
lvl[4]	auto[0]	277	1			T75	4		T183	6		T30	6
lvl[4]	auto[1]	68	1			T51	2		T52	2		T198	2
lvl[8]	auto[0]	330	1			T75	3		T183	5		T30	7
lvl[8]	auto[1]	72	1			T199	2		T200	2		T201	4
lvl[16]	auto[0]	285	1			T75	1		T183	4		T30	3
lvl[16]	auto[1]	22	1			T202	1		T203	21		-	-

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded