Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41088

1

T1

16

T2

606

T3

455

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32830	1			T1	20		T2	137		T3	107
values[0x0]	15828	1			T1	8		T2	239		T3	160
values[0x1]	16639	1			T1	12		T2	317		T3	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48513

1

T1

23

T2

670

T3

479

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	177	1			T3	5		T4	19		T8	1
valid_sources[0x01]	235	1			T3	2		T10	3		T15	7
valid_sources[0x02]	243	1			T3	2		T8	2		T14	1
valid_sources[0x03]	151	1			T3	2		T8	1		T9	3
valid_sources[0x04]	465	1			T3	1		T15	7		T20	1
valid_sources[0x05]	170	1			T3	2		T8	2		T12	1
valid_sources[0x06]	199	1			T3	2		T14	1		T9	1
valid_sources[0x07]	219	1			T3	2		T14	2		T6	11
valid_sources[0x08]	209	1			T3	1		T12	3		T9	1
valid_sources[0x09]	246	1			T3	1		T8	3		T14	1
valid_sources[0x0a]	375	1			T14	1		T9	4		T15	6
valid_sources[0x0b]	409	1			T4	13		T5	103		T9	1
valid_sources[0x0c]	160	1			T3	2		T4	15		T6	5
valid_sources[0x0d]	163	1			T3	2		T8	1		T15	2
valid_sources[0x0e]	301	1			T3	3		T15	4		T22	3
valid_sources[0x0f]	153	1			T3	1		T4	16		T8	1
valid_sources[0x10]	202	1			T3	3		T14	1		T15	4
valid_sources[0x11]	236	1			T3	2		T14	2		T15	4
valid_sources[0x12]	186	1			T3	7		T7	8		T6	5
valid_sources[0x13]	152	1			T3	1		T6	2		T15	10
valid_sources[0x14]	229	1			T3	2		T6	2		T9	2
valid_sources[0x15]	194	1			T3	3		T4	3		T8	1
valid_sources[0x16]	263	1			T3	3		T4	14		T8	2
valid_sources[0x17]	149	1			T15	1		T21	3		T22	4
valid_sources[0x18]	221	1			T1	1		T3	4		T14	1
valid_sources[0x19]	310	1			T3	2		T4	44		T12	1
valid_sources[0x1a]	276	1			T3	3		T4	10		T6	10
valid_sources[0x1b]	117	1			T3	2		T4	4		T14	2
valid_sources[0x1c]	188	1			T1	1		T3	4		T4	1
valid_sources[0x1d]	202	1			T3	3		T9	3		T15	6
valid_sources[0x1e]	168	1			T4	22		T12	1		T15	3
valid_sources[0x1f]	195	1			T3	2		T14	2		T9	2
valid_sources[0x20]	332	1			T14	1		T6	9		T9	2
valid_sources[0x21]	195	1			T3	2		T4	27		T6	12
valid_sources[0x22]	498	1			T3	2		T4	23		T6	17
valid_sources[0x23]	199	1			T3	1		T4	41		T15	3
valid_sources[0x24]	328	1			T3	1		T9	2		T15	10
valid_sources[0x25]	189	1			T3	3		T14	2		T5	12
valid_sources[0x26]	485	1			T1	1		T3	2		T4	37
valid_sources[0x27]	293	1			T3	4		T4	23		T6	2
valid_sources[0x28]	243	1			T14	2		T9	1		T15	6
valid_sources[0x29]	386	1			T3	2		T4	11		T8	2
valid_sources[0x2a]	364	1			T3	2		T4	18		T8	2
valid_sources[0x2b]	215	1			T4	2		T14	5		T15	8
valid_sources[0x2c]	154	1			T3	2		T9	1		T15	4
valid_sources[0x2d]	259	1			T3	3		T9	5		T15	2
valid_sources[0x2e]	320	1			T15	10		T21	7		T44	1
valid_sources[0x2f]	359	1			T3	5		T4	8		T14	2
valid_sources[0x30]	165	1			T8	2		T14	1		T9	1
valid_sources[0x31]	221	1			T3	5		T4	10		T8	7
valid_sources[0x32]	198	1			T3	2		T14	1		T15	11
valid_sources[0x33]	368	1			T3	2		T14	1		T6	5
valid_sources[0x34]	271	1			T3	2		T4	8		T14	3
valid_sources[0x35]	347	1			T3	3		T6	2		T15	4
valid_sources[0x36]	149	1			T3	3		T4	12		T14	2
valid_sources[0x37]	152	1			T3	1		T7	4		T4	8
valid_sources[0x38]	191	1			T3	1		T8	3		T9	3
valid_sources[0x39]	205	1			T1	2		T7	4		T8	5
valid_sources[0x3a]	358	1			T3	3		T6	4		T15	7
valid_sources[0x3b]	154	1			T3	4		T6	4		T9	1
valid_sources[0x3c]	183	1			T4	6		T14	2		T6	3
valid_sources[0x3d]	422	1			T3	2		T4	1		T8	2
valid_sources[0x3e]	389	1			T1	1		T3	2		T6	32
valid_sources[0x3f]	189	1			T3	1		T9	1		T15	1
valid_sources[0x40]	198	1			T1	1		T3	2		T9	5
valid_sources[0x41]	232	1			T3	1		T7	39		T8	1
valid_sources[0x42]	172	1			T3	3		T12	2		T6	9
valid_sources[0x43]	152	1			T3	4		T4	9		T15	6
valid_sources[0x44]	160	1			T1	2		T3	3		T9	3
valid_sources[0x45]	354	1			T4	10		T14	1		T9	3
valid_sources[0x46]	173	1			T3	1		T14	1		T9	3
valid_sources[0x47]	460	1			T3	1		T14	2		T15	2
valid_sources[0x48]	177	1			T3	3		T4	28		T15	3
valid_sources[0x49]	336	1			T4	17		T14	3		T15	14
valid_sources[0x4a]	359	1			T3	2		T4	4		T14	1
valid_sources[0x4b]	301	1			T3	2		T8	2		T15	4
valid_sources[0x4c]	179	1			T3	2		T4	21		T8	1
valid_sources[0x4d]	392	1			T3	1		T7	57		T8	1
valid_sources[0x4e]	381	1			T3	1		T4	8		T15	4
valid_sources[0x4f]	410	1			T3	2		T4	13		T14	2
valid_sources[0x50]	198	1			T3	2		T14	2		T9	2
valid_sources[0x51]	319	1			T2	100		T3	2		T14	1
valid_sources[0x52]	334	1			T3	1		T6	24		T9	2
valid_sources[0x53]	208	1			T3	4		T8	2		T6	10
valid_sources[0x54]	208	1			T4	17		T15	9		T27	3
valid_sources[0x55]	221	1			T3	1		T14	1		T6	5
valid_sources[0x56]	265	1			T3	2		T4	6		T14	2
valid_sources[0x57]	169	1			T3	2		T8	1		T9	1
valid_sources[0x58]	269	1			T3	3		T14	2		T9	4
valid_sources[0x59]	396	1			T1	1		T3	1		T4	35
valid_sources[0x5a]	306	1			T3	1		T9	7		T15	3
valid_sources[0x5b]	381	1			T3	1		T14	1		T15	2
valid_sources[0x5c]	304	1			T3	2		T12	1		T15	4
valid_sources[0x5d]	460	1			T3	2		T7	67		T14	1
valid_sources[0x5e]	183	1			T3	1		T4	17		T14	1
valid_sources[0x5f]	251	1			T3	1		T14	1		T15	5
valid_sources[0x60]	161	1			T3	1		T14	2		T9	2
valid_sources[0x61]	155	1			T1	1		T3	4		T9	3
valid_sources[0x62]	305	1			T3	2		T8	1		T14	1
valid_sources[0x63]	168	1			T3	1		T6	10		T15	13
valid_sources[0x64]	417	1			T1	1		T2	84		T3	2
valid_sources[0x65]	139	1			T1	1		T3	2		T14	2
valid_sources[0x66]	194	1			T3	1		T4	28		T9	3
valid_sources[0x67]	222	1			T3	2		T6	11		T9	1
valid_sources[0x68]	258	1			T1	1		T3	2		T14	1
valid_sources[0x69]	280	1			T3	5		T4	6		T8	1
valid_sources[0x6a]	161	1			T9	1		T15	2		T20	1
valid_sources[0x6b]	442	1			T1	2		T3	2		T14	1
valid_sources[0x6c]	325	1			T3	1		T15	15		T22	1
valid_sources[0x6d]	377	1			T3	3		T7	12		T4	3
valid_sources[0x6e]	177	1			T3	3		T6	13		T9	3
valid_sources[0x6f]	142	1			T3	4		T7	7		T8	2
valid_sources[0x70]	185	1			T3	3		T7	5		T8	1
valid_sources[0x71]	228	1			T3	7		T4	15		T14	1
valid_sources[0x72]	144	1			T1	1		T3	1		T6	1
valid_sources[0x73]	288	1			T3	3		T8	1		T14	1
valid_sources[0x74]	402	1			T1	1		T3	2		T7	4
valid_sources[0x75]	393	1			T3	2		T4	10		T14	1
valid_sources[0x76]	185	1			T3	2		T6	9		T28	1
valid_sources[0x77]	256	1			T4	1		T14	1		T9	1
valid_sources[0x78]	193	1			T1	1		T3	2		T4	10
valid_sources[0x79]	353	1			T1	1		T3	3		T4	5
valid_sources[0x7a]	505	1			T3	1		T12	1		T15	10
valid_sources[0x7b]	241	1			T4	7		T8	1		T15	2
valid_sources[0x7c]	195	1			T3	3		T9	1		T15	6
valid_sources[0x7d]	181	1			T3	3		T14	1		T15	3
valid_sources[0x7e]	349	1			T3	1		T8	4		T15	5
valid_sources[0x7f]	164	1			T3	2		T9	2		T15	4
valid_sources[0x80]	170	1			T3	2		T14	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14778

1

T1

7

T2

136

T3

106

values[0x0]

all_enables

biggest_size

13507

1

T1

5

T2

238

T3

154

values[0x1]

all_enables

biggest_size

12803

1

T1

4

T2

232

T3

195